HOMEWORK REPORT COURSE microprocessor(lab)
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HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY
FACULTY OF ELECTRICAL ELECTRONICS ENGINEERING
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HOMEWORK REPORT
COURSE: Microprocessor(Lab)
CLASS: TT02
INSTRUCTOR: Dr. Nguyễn Trung Hiếu
Nguyễn Huy Khang
1951062
HO CHI MINH CITY, FEBRUARY 2022
Code:
library ieee;
use ieee.std_logic_1164.all;
entity halfadder is
port(
x, y : in std_logic;
s, c : out std_logic
);
end halfadder;
architecture subprogram1 of halfadder is
begin
s <= x xor y;
c <= x and y;
end subprogram1;
library ieee;
use ieee.std_logic_1164.all;
entity multiplication_block is
port(
a, b : in std_logic_vector(1 downto 0);
c : out std_logic_vector(3 downto 0)
);
end multiplication_block;
architecture subprogram2 of multiplication_block is
component halfadder
port(
x, y : in std_logic;
s, c : out std_logic
);
end component;
signal wire : std_logic;
begin
c(0) <= a(0) and b(0);
adder1 : halfadder port map (a(1) and b(0), a(0) and b(1), c(1), wire);
adder2 : halfadder port map (a(1) and b(1), wire, c(2), c(3));
end subprogram2;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity half_matrix is
port(
a1, a2, a3 : in std_logic_vector(1 downto 0);
b1, b2, b3 : in std_logic_vector(1 downto 0);
c : out std_logic_vector(5 downto 0)
);
end half_matrix;
architecture subprogram3 of half_matrix is
component multiplication_block
port(
a, b : in std_logic_vector(1 downto 0);
c : out std_logic_vector(3 downto 0)
);
end component;
signal num1, num2, num3 : std_logic_vector(3 downto 0);
signal num4 : std_logic_vector(4 downto 0);
begin
multiplication1 : multiplication_block port map (a1, b1, num1);
multiplication2 : multiplication_block port map (a2, b2, num2);
multiplication3 : multiplication_block port map (a3, b3, num3);
process(num1, num2, num3, num4)
begin
num4 <= ('0' & num1) + num2;
c <= ('0' & num4) + num3;
end process;
end subprogram3;
library ieee;
use ieee.std_logic_1164.all;
entity full_matrix_multiplication is
port(
a1, a2, a3, a4, a5, a6, a7, a8, a9 : in std_logic_vector(1 downto 0);
b1, b2, b3, b4, b5, b6, b7, b8, b9 : in std_logic_vector(1 downto 0);
c1, c2, c3, c4, c5, c6, c7, c8, c9 : out std_logic_vector(5 downto 0)
);
end full_matrix_multiplication;
architecture subprogram4 of full_matrix_multiplication is
component half_matrix
port(
a1, a2, a3 : in std_logic_vector(1 downto 0);
b1, b2, b3 : in std_logic_vector(1 downto 0);
c : out std_logic_vector(5 downto 0)
);
end component;
begin
stage1 : half_matrix port map (a1, a2, a3, b1, b2, b3, c1);
stage2 : half_matrix port map (a4, a5, a6, b1, b2, b3, c2);
stage3 : half_matrix port map (a7, a8, a9, b1, b2, b3, c3);
stage4 : half_matrix port map (a1, a2, a3, b4, b5, b6, c4);
stage5 : half_matrix port map (a4, a5, a6, b4, b5, b6, c5);
stage6 : half_matrix port map (a7, a8, a9, b4, b5, b6, c6);
stage7 : half_matrix port map (a1, a2, a3, b7, b8, b9, c7);
stage8 : half_matrix port map (a4, a5, a6, b7, b8, b9, c8);
stage9 : half_matrix port map (a7, a8, a9, b7, b8, b9, c9);
end subprogram4;
library ieee;
use ieee.std_logic_1164.all;
entity <PROJECT3> is
port(
address : inout std_logic;
a1, a2, a3, a4, a5, a6, a7, a8, a9 : in std_logic_vector(1 downto 0);
b1, b2, b3, b4, b5, b6, b7, b8, b9 : in std_logic_vector(1 downto 0);
c1, c2, c3, c4, c5, c6, c7, c8, c9 : out std_logic_vector(5 downto 0);
clock, reset, write_n, chipselect : in std_logic;
start : in std_logic;
data_read, done : out std_logic
);
end <PROJECT3>;
architecture subprogram5 of <PROJECT3> is
component full_matrix_multiplication
port(
a1, a2, a3, a4, a5, a6, a7, a8, a9 : in std_logic_vector(1 downto 0);
b1, b2, b3, b4, b5, b6, b7, b8, b9 : in std_logic_vector(1 downto 0);
c1, c2, c3, c4, c5, c6, c7, c8, c9 : out std_logic_vector(5 downto 0)
);
end component;
type memmory1 is array(8 downto 0) of std_logic_vector(1 downto 0);
type memmory2 is array(8 downto 0) of std_logic_vector(5 downto 0);
type fsm_state_type is (state0, state1, state2, state3, state4);
signal state : fsm_state_type;
signal trigger : std_logic;
signal a : memmory1;
signal b : memmory1;
signal c : memmory2;
begin
multi_process: full_matrix_multiplication port map (
a1 => a(0),
a2 => a(1),
a3 => a(2),
a4 => a(3),
a5 => a(4),
a6 => a(5),
a7 => a(6),
a8 => a(7),
a9 => a(8),
b1 => b(0),
b2 => b(3),
b3 => b(6),
b4 => b(1),
b5 => b(4),
b6 => b(7),
b7 => b(2),
b8 => b(5),
b9 => b(8),
c1 => c(0),
c2 => c(3),
c3 => c(6),
c4 => c(1),
c5 => c(4),
c6 => c(7),
c7 => c(2),
c8 => c(5),
c9 => c(8));
process(clock, reset, start)
begin
if (reset = '1') then
state <= state0;
data_read <= '0';
done <= '0';
elsif (rising_edge(clock)) then
if start = '1' then
trigger <= '1';
end if;
case state is
when state0 =>
if (trigger = '1' and write_n = '1' and chipselect = '1') then
state <= state1;
data_read <= '0';
done <= '0';
elsif (trigger = '1' and write_n = '0' and chipselect = '1') then
state <= state3;
data_read <= '0';
done <= '0';
end if;
when state1 =>
if (trigger = '1' and write_n = '1' and chipselect = '1') then
state <= state2;
data_read <= '1';
done <= '0';
a(0) <= a1;
a(1) <= a2;
a(2) <= a3;
a(3) <= a4;
a(4) <= a5;
a(5) <= a6;
a(6) <= a7;
a(7) <= a8;
a(8) <= a9;
b(0) <= b1;
b(1) <= b2;
b(2) <= b3;
b(3) <= b4;
b(4) <= b5;
b(5) <= b6;
b(6) <= b7;
b(7) <= b8;
b(8) <= b9;
else
state <= state0;
data_read <= '0';
done <= '0';
end if;
when state2 =>
state <= state4;
data_read <= '0';
done <= '1';
c1 <= c(0);
c2 <= c(1);
c3 <= c(2);
c4 <= c(3);
c5 <= c(4);
c6 <= c(5);
c7 <= c(6);
c8 <= c(7);
c9 <= c(8);
when state4 =>
trigger <= '0';
state <= state0;
data_read <= '0';
done <= '0';
when state3 =>
state <= state0;
data_read <= '0';
done <= '0';
end case;
end if;
end process;
end subprogram5;
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