© 2002 by Xilinx, Inc. All rights reserved.
Architecture
For Academic Use Only
For Academic Use Only
Spartan-IIE Technical Details

Table of Contents
Spartan-IIE Overview
Embedded Memory
System Clock Management
Interfaces – Select I/O
Logic and Routing
Configuration Solutions
For Academic Use Only
For Academic Use Only
Virtex-II
CPLDs
Low Power
FPGAs
SRAM-based
Feature Rich
High Performance
Spartan-IIE
Density (System Gates)
Features
FPGAs
SRAM-based
Feature Rich
Low Cost
10K 600K 10M
Xilinx

Your Programmable Logic Solution
For Academic Use Only
For Academic Use Only
Memory Resources
SRL16 registers
Distributed Memory
Block Memory
External Memory
System Clock
Management
Digital Delay Lock
Loops (DLLs)
I/O Connectivity
SelectIO
TM
Technology
Support major I/O standards

Logic & Routing
Flexible logic implementation
Vector Based Routing
Internal 3-State bussing
The Spartan-IIE Solution
More Than Just Silicon
. . .
. . .
. . .
. . .
I
O

B
I
O
B
I
O
B
I
O
B
CLB CLB
R
A
M
R
A
M
R
A
M
R
A
M
IOBIOB
DLLDLL
CLB CLB
DLL
IOB IOB
DLL
For Academic Use Only

For Academic Use Only
System Clock
Management
System Interfaces
Logic & Routing
Configuration
Embedded
Memory
Spartan-IIE Features
For Academic Use Only
For Academic Use Only
Logic & Routing
Spartan-IIE Features
For Academic Use Only
For Academic Use Only
Logic & Routing
CLB Array
•
Configurable for simple to complex logic
•
Excellent for fast arithmetic operations
•
Flexible for logic or distributed RAM
implementations
•
Predictable routing delays
•
Core-friendly architecture
•
Quick Place and Route times

•
Internal 3-state bussing
Configurable Logic Block (CLB)
For Academic Use Only
For Academic Use Only
Logic Advantages
•
Look Up Table (LUT) versatility
–
CLB primary building block
–
Flexible for logic or distributed RAM implementation
•
Fast arithmetic operations
–
Specialized Carry Logic for arithmetic operations
–
Fast DSP functions FIR filters
•
Configurable for simple to complex logic
–
Allow up to 6 input functions into a one logic level
For Academic Use Only
For Academic Use Only
F5IN
CIN
CLK
CE
COUT
D

Q
CK
S
R
EC
D
Q
CK
R
EC
O
G4
G3
G2
G1
Look-Up
Table
Carry
&
Control
Logic
O
YB
Y
F4
F3
F2
F1
XB
X

Look-Up
Table
BY
SR
S
Carry
&
Control
Logic
SLICE
COUT
D
Q
CK
S
R
EC
D
Q
CK
R
EC
O
G4
G3
G2
G1
Look-Up
Table
Carry

&
Control
Logic
O
YB
Y
F4
F3
F2
F1
XB
X
Look-Up
Table
F5IN
BY
SR
S
Carry
&
Control
Logic
CIN
CLK
CE
SLICE
CLB Structure
•
Each slice has 2 LUT-FF pairs with associated carry logic
•

Two 3-state buffers (BUFT) associated with each CLB, accessible
by all CLB outputs
For Academic Use Only
For Academic Use Only
CLB Slice Structure
•
Each slice contains two sets of the following:
–
Four-input LUT
•
Any 4-input logic function
•
Or 16-bit x 1 sync RAM
•
Or 16-bit shift register
–
Carry & Control
•
Fast arithmetic logic
•
Multiplier logic
•
Multiplexer logic
–
Storage element
•
Latch or flip-flop
•
Set and reset
•

True or inverted inputs
•
Sync. or async. control
For Academic Use Only
For Academic Use Only
Inputs(ABCD) Output(Z)
0000 0
0001 0
0010 1
0011 0
……
1110 1
1111 1
Truth Table
LUT
=
4-input logic function
C
D
Z
A
B
Four-Input LUT
•
Implements combinatorial logic
–
Any 4-input logic function
–
Cascaded for wide-input functions
For Academic Use Only

For Academic Use Only
CLB
MUXF6
Slice
LUT
LUT
MUXF5
Slice
LUT
LUT
MUXF5
Dedicated Expansion
Multiplexers
•
MUXF5 combines 2 LUTs to create
–
4x1 multiplexer
–
Or any 5-input function (LUT5)
–
Or selected functions up to 9 inputs
•
MUXF6 combines 2 slices to form
–
8x1 multiplexer
–
Or any 6-input function (LUT6)
–
Or selected functions up to 19 inputs
•

Dedicated muxes are faster and
more space efficient
For Academic Use Only
For Academic Use Only
RAM16X1S
O
D
WE
WCLK
A0
A1
A2
A3
RAM32X1S
O
D
WE
WCLK
A0
A1
A2
A3
A4
RAM16X2S
O1
D0
WE
WCLK
A0
A1

A2
A3
D1
O0
=
=
LUT
LUT
or
LUT
RAM16X1D
SPO
D
WE
WCLK
A0
A1
A2
A3
DPRA0 DPO
DPRA1
DPRA2
DPRA3
or
Distributed RAM
•
CLB LUT configurable as
Distributed RAM
–
A LUT equals 16x1 RAM

–
Implements Single and Dual-Ports
–
Cascade LUTs to increase RAM size
•
Synchronous write
•
Synchronous/Asynchronous read
–
Accompanying flip-flops used for
synchronous read
For Academic Use Only
For Academic Use Only
D Q
CE
D Q
CE
D Q
CE
D Q
CE
LUT
IN
CE
CLK
DEPTH[3:0]
OUT
LUT
=
Shift Register

•
Each LUT can be configured
as shift register
–
Serial in, serial out
•
Dynamically addressable
delay up to 16 cycles
•
For programmable pipeline
•
Cascade for greater cycle
delays
•
Use CLB flip-flops to add
depth
For Academic Use Only
For Academic Use Only
Shift Register
•
Register-rich FPGA
–
Allows for addition of pipeline stages to increase throughput
•
Data paths must be balanced to keep desired functionality
64
Operation A
4 Cycles 8 Cycles
Operation B
3 Cycles

Operation C
64
12 Cycles
3 Cycles
9-Cycle imbalance
For Academic Use Only
For Academic Use Only
12 Cycles
64
Operation A
4 Cycles 8 Cycles
Operation B
3 Cycles
Operation C
12 Cycles
Paths statically
balanced
9 Cycles
Pipeline
64
Shift Register
•
LUT as shift register
–
Used to add pipeline stages
•
Increase overall register count
–
16 bit shift register per LUT
–

64 bit shift register per CLB
For Academic Use Only
For Academic Use Only
CLB Arithmetic Logic
•
Dedicated carry logic
–
Provides high performance for
counters & arithmetic functions
–
Discrete XOR component for
single level sum completion
–
Two separate carry chains in CLB
allow for 3 operand functions
–
Can also be used to cascade LUTs for wide-input logic
functions
Single-level Sum
LUT
0 1
LUT
0 1
LUT
0 1
LUT
0 1
For Academic Use Only
For Academic Use Only
COUT

Look-Up
Table
SLICE0
CIN
COUT
O
Look-Up
Table
Carry
&
Control
Logic
Look-Up
Table
SLICE1
CIN
CLB
Look-Up
Table
A1
B1
A0
B0
C1
C0
SUM1
SUM0
PARTIAL0
PARTIAL1
Carry

&
Control
Logic
Carry
&
Control
Logic
Carry
&
Control
Logic
3 Operand Adder Function
•
A, B, C are two-bits wide
–
SUM = A + B + C or PARTIAL + C, where PARTIAL = A + B
–
Implementation
•
First 2-operand sum ‘A+B’ is performed in Slice 0
•
Second 2-operand sum ‘PARTIAL + C’ is performed in Slice 1
–
Fast local feedback connection within the CLB
•
Very small delay for on PARTIAL
For Academic Use Only
For Academic Use Only
Carry Logic for
Wide Input Functions

•
Higher performance
•
Efficient resource utilization
•
Common applications
–
Wide input decoding
–
Comparators
•
HDL design entry
–
LUT can be inferred
–
MUXCY must be instantiated
For Academic Use Only
For Academic Use Only
12- Input AND Function
•
Utilization
–
3 LUTs and 3 MUXCYs
–
As opposed to 4 LUTs
•
Performance
–
1 logic level
–

As opposed to 2 logic levels
0 1
INIT=8000
0 1
INIT=8000
0 1
INIT=8000
Output
Vcc
LUT1
LUT2
LUT3
D
C
B
A
H
G
F
E
L
K
J
I
MUXCY
MUXCY
MUXCY
4-Input AND Truth Table
Inputs(ABCD) Output(Z) Output(HEX)
0000 0

0001 0
0010 0
0011 0
……
1011 0
1100 0
1101 0
1110 0
1111 1
0
8
For Academic Use Only
For Academic Use Only
12- Input OR Function
0 1
INIT=0001
0 1
INIT=0001
0 1
INIT=0001
Vcc
Vcc
Vcc
Output
LUT1
LUT2
LUT3
D
C
B

A
H
G
F
E
L
K
J
I
MUXCY
MUXCY
MUXCY
4-Input NOR Truth Table
Inputs(ABCD) Output(Z) Output(HEX)
0000 1
0001 0
0010 0
0011 0
……
1011 0
1100 0
1101 0
1110 0
1111 0
1
0
•
Utilization
–
3 LUTs and 3 MUXCYs

–
As opposed to 4 LUTs
•
Performance
–
1 logic level
–
As opposed to 2 logic levels
For Academic Use Only
For Academic Use Only
CO
DI CI
S
LUT
CY_MUX
CY_XOR
MULT_AND
A
B
A x B
Dedicated AND gate
Dedicated CLB Multiplier
Logic
•
Dedicated AND gate
•
Highly efficient ‘Shift & Add’ implementation
–
For a 16x16 Multiplier
•

30% reduction in area and one less logic level
For Academic Use Only
For Academic Use Only
Lower Operating Power
•
1.8V core supply
–
Reduces power consumption
•
Advanced signaling standards
–
Smaller voltage transitions
–
Reduces switching power
•
DLLs reduce clock speed requirements
–
Faster clock propagation
–
Internal multiplication of clock
–
Reduces power on clock nets
For Academic Use Only
For Academic Use Only
Logic Summary
•
Flexible Configurable Logic Block (CLB) implementations
–
Logic
–

Distributed RAM
–
Shift register
•
CLB configurable for simple to complex logic
–
Any 6 input function into one logic level
•
Excellent for fast arithmetic operations
–
Specialized carry logic for arithmetic operations
–
Fast DSP functions FIR filters
For Academic Use Only
For Academic Use Only
Logic & Routing
Spartan-IIE Features