Slide điện tử từ trường lecture 8 mosfet circuit
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Lecture 08
MOSFET’s Circuit
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topics
1. Large-signal operation
2. FET circuits at DC
3. FET biasing schemes
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Large-signal operation
ID =
μCo w
2L
(vGS − Vt ) 2
Load line: VDD
k n' w
2
ID =
(vGS − Vt )
2L
= iD RD + vDS
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dvo
Av ≡
dvI
v I =VIQ
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Example 4.2
DC analysis
ID =
Given I = 0.4mA
D
VD = 0.5V
Vt = 0.7V
μ nCox = 100 μA / V 2
L = 1μm
w = 32 μm
μC o w
⇒ vGS
(vGS − Vt ) 2
2L
= 1.2V
VS = I D RS + VSS
⇒ VS = I D RS − 2.5V
− 1.2 + 2.5
Rs =
= 3.25k
0.4m
VDD = I D RD + VD
RD = ?
⇒ 2.5V = I D RD + VD
RS = ?
RD =
2.5 − 0.5
= 5k
0.4m
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Example 4.3
Given
I D = 80 μA
Vt = 0.6V
μ nCox = 200 μA / V 2
L = 0. 8 μ m
w = 4 μm
VD = ?
R=?
ID =
μC o w
2L
⇒ VD = 1V
(VD − Vt ) 2
VDD = 3V = I D R + VD
3 −1
⇒R=
= 25k
0.08m
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Exercise 4.12
ID
R = 25k
VD 2
ID =
μC o w
(VGS 2 − Vt ) 2 =
2L
QVD = 1V ∴ I D = 80μA
μC o w
2L
(VD − Vt ) 2
VDD = 3V = I D R2 + VD 2
⇒ VD 2 = 3 − 80 μ × 20k = 1.4V
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Example 4.4
let
Vt = 1V
K n′ (W / L) = 1mA / V 2
find
RD = ?
vDS = VD = 0.1V ≤ VDD − Vt = 5 − 1 = 4
vDS ≤ vGS − Vt → ohmic region
ID =
μ n Co w
2
[2(vGS − Vt )vDS − vDS
]
2L
→ I D = 0.395mA
5 − 0.1
RD =
= 12.4k
0.395m
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Example 4.5
let
Vt = 1V
K n′ (W / L) = 1mA / V 2
Assume FET
in saturation
mode since
VG>0
10 M
10V = 5V
10 M + 10M
1 W
I D = k n'
(VGS − Vt ) 2
2 L
1
⇒ I D = × 1× [(5 − I D × 6k ) − 1]2
2
⇒ 18I D2 − 25I D + 8 = 0
VG =
I D = 0.89mA, I D = 0.5mA
if
I D = 0.89mA
VS = 6k × 0.89m = 5.34V
→ VGS < 0
if
contradiction
I D = 0.5mA
VS = 6k × 0.5m = 3V
→ VGS = 2V
→ VD = 10 − 6k × 0.5m = 7V
→ VD > VG − Vt
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Example 4.6
Design the circuit operate in saturation
Find the range of RD
1 'W
k n (VGS − Vt ) 2
2 L
1
⇒ 0.5 = ×1× [VGS − (−1)]2
2
⇒ VGS = −2V
ID =
VDS ≥ VGS − Vt = −2 + 1 = −1
⇒ VD (max) = +4V
4
= 8k
0.5m
3
=
= 6k
0.5m
RD (max) =
RD (min)
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Example 4.7
let
Vnt = −V pt = 1V
K n′ (W / L)
= K ′p (W / L) = 1mA / V 2
First case : vI=0V
Q p on, Qn on
VGS ( p ) = −2.5V
VGS ( n ) = 2.5V
vo = 0V
1
I DP = ×1[−2.5 − (−1)]2 = 1.125mA
2
1
I Dn = × 1[2.5 − 1]2 = 1.125mA
2
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Second case : vI=+2.5V
Qp
ID =
μ n Co w
2L
off , Qn
2
[2(vGS − Vt )vDS − vDS
]≈
ohmic region
μ n Co w
L
(vGS − Vt )vDS
NOT gate
VD = −2.44V = vo
VGS = 5V
I Dn = 1×1[5 − 1]VDS
VDS = −2.44 + 2.5 = 0.06
= 1×1[5 − 1](− I Dn ×10k )
VGS − Vt = 5 − 1 = 4
⇒ I Dn = 0.244mA
VDS ≤ VGS − Vt
Ohmic region
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Second case : vI=-2.5V
Qp
ohmic region , Qn
off
NOT gate
VSG = 5V
I Dp = 1×1[5 − 1]VSD
VD = vo = I Dp × 10k = 2.44V
VSD = +2.5 − 2.44 = 0.06
= 1×1[5 − 1](2.5 − I Dp × 10k ) V − V = 5 − 1 = 4
SG
t
⇒ I Dp = 0.244mA
VSD ≤ VSG − Vt Ohmic region
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Exercise 4.16 Amplifier
Qn up
Assume
k n' (Wn / Ln ) = k p' (W p / L p ) = 1(mA / V 2 )
Vtn = −Vtp = 1V
λ =0
find
iDN , iDP , vo
for
vI = 0V ,2.5V ,−2.5V
First case : vI=0V
Qn
off
Qp
2nd case : vI=2.5V
3rd case : vI=-2.5V
Qn
Qn
on Q p
off
off
Qp
on
off
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Biasing method
•
•
•
•
Fixed Bias by VGS
Self Bias
Biasing using Drain –to-Gate feedback resistor
Biasing using constant current source
Biasing circuit
Small signal
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ID =
μ n Co w
2L
(vGS − Vt ) 2
1. Device change ( Vt , Cox ,W L )
2. Temperature change ( Vt , μ n
)
Change ID
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Example 4.9
Self Bias
find
Vt = 1.5V
Change MOSFET
K n′ (W / L) = 1mA / V 2
ΔI D = ? mA
k n' w
1
2
ID =
(vGS − Vt ) = × 1× (vGS − 1.5) 2
2
2L
vGS = 7 − 10k × I D
⇒ I D = 0.455mA
when
Good biasing scheme
Vt = 1V
K n′ (W / L) = 1mA / V 2
I D = 0.5mA
I D ↑⇒ I D RS ↑⇒QVG fixed ⇒ VGS ↓
k n' W
Q ID =
(vGS ↓ −Vt ) 2 ⇒ I D ↓
2L
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Self Bias
I D ↑⇒ VS ↑⇒ VGS ↓⇒ I D ↓
Good biasing scheme
'
n
k w
ID =
(vGS − Vt ) 2
2L
VGS = − I D RS
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Exercise 4.21
Drain –to-Gate feedback bias
k n' w
(VGS − Vt ) 2
ID =
2L
1
0.5m = × 1× (VGS − 1) 2
2
⇒ VGS = 2V
parameters
VDD = 5V
Vt = 1V
K n′ (W / L) = 1mA / V 2
requirement
VGS = VDS = VDD − I D RD
I D = 0.5mA
VGS = VDS = 5 − I D × RD
find
2V = 5 − 0.5 × RD
RD , VD
⇒ RD = 6k
VGS = VDS ⇒ saturation
I D ↑⇒ VD = VDD − I D RD ⇒ VD ↓
⇒ VGS ⇒ I D ↓
Good biasing scheme
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Constant current bias
I REF = I D1 =
VDD − VGS
= I D2
R
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