The Thumb Instruction Set
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A6-19
6.6.3 List of Load and Store Multiple instructions
The following instructions follow the formats shown above.
LDMIA Load Multiple. See LDMIA on page A7-40.
POP Pop Multiple. See POP on page A7-75.
PUSH Push Multiple. See PUSH on page A7-78.
STMIA Store Multiple. See STMIA on page A7-84.
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The Thumb Instruction Set
A6-20
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
6.7 Exception-generating instructions
The Thumb instruction set provides two types of instruction whose main purpose is to cause a processor
exception to occur:
• The Software Interrupt (SWI) instruction is used to cause a SWI exception to occur (see Software
Interrupt exception on page A2-16). This is the main mechanism in the Thumb instruction set by
which User mode code can make calls to privileged Operating System code.
• The Breakpoint (BKPT) instruction is used for software breakpoints in T variants of ARM
architecture versions 5 and above. Its default behavior is to cause a Prefetch Abort exception to occur
(see Prefetch Abort (instruction fetch memory abort) on page A2-16). A debug monitor program that
has previously been installed on the Prefetch Abort vector can handle this exception.
If debug hardware is present in the system, it is allowed to override this default behavior. Details of
whether and how this happens are
IMPLEMENTATION DEFINED.
6.7.1 Instruction encodings
SWI <immed_8>
BKPT <immed_8>

In both SWI and BKPT, the immed_8 field of the instruction is ignored by the ARM processor. The SWI or
Prefetch Abort handler can optionally be written to load the instruction that caused the exception and extract
these fields. This allows them to be used to communicate extra information about the Operating System call
or breakpoint to the handler.
6.7.2 List of exception-generating instructions
BKPT Breakpoint. See BKPT on page A7-24.
SWI Software Interrupt. See SWI on page A7-102.
15 14 13 12 11 10 9 8 7 0
11011111 immed_8
15 14 13 12 11 10 9 8 7 0
10111110 immed_8
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The Thumb Instruction Set
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A6-21
6.8 Undefined instruction space
The following instructions are UNDEFINED in the Thumb instruction set:
In general, these instructions can be used to extend the Thumb instruction set in the future. However, it is
intended that the following group of instructions will not be used in this manner:
Use one of these instructions if you want to use an undefined instruction for software purposes, with
minimal risk that future hardware will treat it as a defined instruction.
1514131211109876543210
10110001xxxxxxxx
10110x1xxxxxxxxx
101110xxxxxxxxxx
10111111xxxxxxxx
11011110xxxxxxxx
1514131211109876543210
11011110xxxxxxxx

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The Thumb Instruction Set
A6-22
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
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ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-1
Chapter A7
Thumb Instructions
This chapter describes the syntax and usage of every Thumb instruction, in the section:
• Alphabetical list of Thumb instructions on page A7-2
• Thumb instructions and architecture versions on page A7-104.
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Thumb Instructions
A7-2
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1 Alphabetical list of Thumb instructions
Every Thumb instruction is listed on the following pages. Each instruction description shows:
• the instruction encoding
• the instruction syntax
• the versions of the ARM architecture where the instruction is valid
• any exceptions that might apply
• a pseudo-code specification of how the instruction operates
• notes on usage and special cases
• the equivalent ARM instruction encoding.
7.1.1 General notes
These notes explain the types of information and abbreviations used on the instruction pages.

Syntax abbreviations
The following abbreviations are used in the instruction pages:
immed_<n> This is an <n>-bit immediate value. For example, an 8-bit immediate value is represented
by:
immed_8
signed_immed_<n>
This is a signed immediate. For example, an 8-bit signed immediate is represented by:
signed_immed_8
Architecture version
For the convenience of the reader, this section describes the version of the ARM instruction set that the
instruction is associated with, not the version of the Thumb instruction set. There have been two versions
of the Thumb instruction set architecture to date:
THUMBv1 This is used in T variants of version 4 of the ARM instruction set architecture.
THUMBv2 This is used in T variants of version 5 and above of the ARM instruction set architecture.
Instructions which are described as being in all T variants are therefore present in both THUMBv1 and
THUMBv2, while those that are described as being in T variants of version 5 and above are in THUMBv2
only.
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-3
Equivalent ARM syntax and encoding
This section shows the syntax and encoding of an equivalent ARM instruction. When no precise equivalent
is available, a close equivalent is shown and the reasons why it is not a precise equivalent are explained.
A common reason for the instruction not being a precise equivalent is that it reads the value of the PC. This
produces the instruction’s own address plus N, where N is 8 for ARM instructions and 4 for Thumb
instructions. This difference can often be compensated for by adjusting an immediate constant in the
equivalent ARM instruction.
In the equivalent instruction encodings, named fields and bits must be filled in with the corresponding fields

and bits from the Thumb instruction, or in a few cases with values derived from the Thumb instruction as
described in the text.
The ARM instruction fields are normally the same length as the corresponding Thumb instruction fields,
with one important exception. Thumb register fields are normally 3 bits long, whereas ARM register fields
are normally 4 bits long. In these cases, the Thumb register field must be extended with a high-order 0 when
substituted into the ARM register field, so that the ARM instruction refers to the correct one of R0 to R7.
Information on usage
Usage information is only given for Thumb instructions where it differs significantly from ARM instruction
usage. If no Usage section appears for a Thumb instruction, see the equivalent ARM instruction page in
Chapter A4 ARM Instructions for usage information.
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Thumb Instructions
A7-4
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.2 ADC
The ADC (Add with Carry) instruction can be used to synthesize multi-word addition. The condition code
flags are updated, based on the result.
Syntax
ADC <Rd>, <Rm>
where:
<Rd> Holds the first value for the addition, and is the destination register for the operation.
<Rm> Specifies the register that contains the second operand for the addition.
Architecture version
All T variants
Exceptions
None
Operation
Rd = Rd + Rm + C Flag
N Flag = Rd[31]

Z Flag = if Rd == 0 then 1 else 0
C Flag = CarryFrom(Rd + Rm + C Flag)
V Flag = OverflowFrom(Rd + Rm + C Flag)
Equivalent ARM syntax and encoding
ADCS <Rd>, <Rd>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0100000101 Rm Rd
31302928272625242322212019 1615 1211109876543 0
111000001011 Rd Rd 00000000 Rm
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-5
7.1.3 ADD (1)
This form of ADD adds a small constant value to the value of a register and stores the result in a second
register. The condition code flags are updated, based on the result.
Syntax
ADD <Rd>, <Rn>, #<immed_3>
where:
<Rd> Is the destination register for the completed operation.
<Rn> Specifies the register that contains the operand for the addition.
<immed_3> Specifies a 3-bit immediate value that is added to the value of <Rn>.
Architecture version
All T variants
Exceptions
None
Operation
Rd = Rn + immed_3
N Flag = Rd[31]

Z Flag = if Rd == 0 then 1 else 0
C Flag = CarryFrom(Rn + immed_3)
V Flag = OverflowFrom(Rn + immed_3)
Equivalent ARM syntax and encoding
ADDS <Rd>, <Rn>, #<immed_3>
15 14 13 12 11 10 9 8 6 5 3 2 0
0001110 immed_3 Rn Rd
31302928272625242322212019 1615 12111098765432 0
111000101001 Rn Rd 000000000immed_3
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Thumb Instructions
A7-6
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.4 ADD (2)
This form of ADD adds a large immediate value to the value of a register and stores the result back in the
same register. The condition code flags are updated, based on the result.
Syntax
ADD <Rd>, #<immed_8>
where:
<Rd> Holds the first operand for the addition, and is the destination register for the
completed operation.
<immed_8> Specifies an 8-bit immediate value that is added to the value of <Rd>.
Architecture version
All T variants
Exceptions
None
Operation
Rd = Rd + immed_8
N Flag = Rd[31]

Z Flag = if Rd == 0 then 1 else 0
C Flag = CarryFrom(Rd + immed_8)
V Flag = OverflowFrom(Rd + immed_8)
Equivalent ARM syntax and encoding
ADDS <Rd>, <Rd>, #<immed_8>
15 14 13 12 11 10 8 7 0
00110 Rd immed_8
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 0
111000101001 Rd Rd 0000 immed_8
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-7
7.1.5 ADD (3)
This form of ADD adds the value of one register to the value of a second register, and stores the result in a
third register. The condition code flags are updated, based on the result.
Syntax
ADD <Rd>, <Rn>, <Rm>
where:
<Rd> Is the destination register for the completed operation.
<Rn> Specifies the register containing the first value for the addition.
<Rm> Specifies the register containing the second value for the addition.
Architecture version
All T variants
Exceptions
None
Operation
Rd = Rn + Rm
N Flag = Rd[31]

Z Flag = if Rd == 0 then 1 else 0
C Flag = CarryFrom(Rn + Rm)
V Flag = OverflowFrom(Rn + Rm)
Equivalent ARM syntax and encoding
ADDS <Rd>, <Rn>, <Rm>
15 14 13 12 11 10 9 8 6 5 3 2 0
0001100 Rm Rn Rd
31302928272625242322212019 1615 1211109876543 0
111000001001 Rn Rd 00000000 Rm
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Thumb Instructions
A7-8
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.6 ADD (4)
This form of ADD adds the values of two registers, one or both of which are high registers. Unlike the
low-register ADD instruction (ADD (3) on page A7-7), this instruction does not change the flags.
Syntax
ADD <Rd>, <Rm>
where:
<Rd> Specifies the register containing the first value, and is also the destination register. It can be
any of R0 to R15. The register number is encoded in the instruction in H1 (most significant
bit) and Rd (remaining three bits).
<Rm> Specifies the register containing the second value. It can be any of R0 to R15. Its number is
encoded in the instruction in H2 (most significant bit) and Rm (remaining three bits).
Architecture version
All T variants
Exceptions
None
Operation

Rd = Rd + Rm
Notes
Operand restriction If a low register is specified for <Rd> and Rm (H1==0 and H2==0), the result is
UNPREDICTABLE.
15 14 13 12 11 10 9 8 7 6 5 3 2 0
01000100H1H2 Rm Rd
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-9
Equivalent ARM syntax and encoding
A close equivalent is:
ADD <Rd>, <Rd>, <Rm>
There are slight differences when the instruction accesses the PC, because of the different definitions of the
PC when executing ARM and Thumb code.
3130292827262524232221201918 161514 12111098765432 0
111000001000H1 Rd H1 Rd 00000000H2 Rm
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Thumb Instructions
A7-10
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.7 ADD (5)
This form of ADD adds an immediate value to the PC and writes the resulting PC-relative address to a
destination register. The immediate can be any multiple of 4 in the range 0 to 1020. The condition codes are
not affected.
Syntax
ADD <Rd>, PC, #<immed_8> * 4
where:

<Rd> Is the destination register for the completed operation.
PC Indicates PC-relative addressing.
<immed_8> Specifies an 8-bit immediate value that is quadrupled and added to the value of the PC.
Architecture version
All T variants
Exceptions
None
Operation
Rd = (PC AND 0xFFFFFFFC) + (immed_8 << 2)
Equivalent ARM syntax and encoding
A close equivalent is:
ADD <Rd>, PC, #<immed_8> * 4
The definitions of the PC differ between ARM and Thumb code. This makes a difference between the
precise results of the instructions.
15 14 13 12 11 10 8 7 0
10100 Rd immed_8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 7 0
1110001010001111 Rd 1111 immed_8
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-11
7.1.8 ADD (6)
This form of ADD adds an immediate value to the SP and writes the resulting SP-relative address to a
destination register. The immediate can be any multiple of 4 in the range 0 to 1020. The condition codes are
not affected.
Syntax
ADD <Rd>, SP, #<immed_8> * 4
where:

<Rd> Is the destination register for the completed operation.
SP Indicates SP-relative addressing.
<immed_8> Specifies an 8-bit immediate value that is quadrupled and added to the value of the SP.
Architecture version
All T variants
Exceptions
None
Operation
Rd = SP + (immed_8 << 2)
Equivalent ARM syntax and encoding
ADD <Rd>, SP, #<immed_8> * 4
15 14 13 12 11 10 8 7 0
10101 Rd immed_8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 7 0
1110001010001101 Rd 1111 immed_8
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Thumb Instructions
A7-12
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.9 ADD (7)
This form of ADD increments the SP by four times a 7-bit immediate (that is, by a multiple of 4 in the range
0 to 508). The condition codes are not affected.
Syntax
ADD SP, #<immed_7> * 4
where:
SP Contains the first operand for the addition. SP is also the destination register for the
operation.
<immed_7> Specifies the immediate value that is quadrupled and added to the value of the SP.
Architecture version

All T variants
Exceptions
None
Operation
SP = SP + (immed_7 << 2)
Usage
For the Full Descending stack which the Thumb instruction set is designed to use, incrementing the SP is
used to discard data on the top of the stack.
Notes
Alternative syntax This instruction can also be written as ADD SP, SP, #(<immed_7> * 4).
Equivalent ARM syntax and encoding
ADD SP, SP, #<immed_7> * 4
15 14 13 12 11 10 9 8 7 6 0
101100000 immed_7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 0
1110001010001101110111110 immed_7
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-13
7.1.10 AND
The AND (Logical AND) instruction performs a bitwise AND of the values in two registers. The condition
code flags are updated, based on the result.
Syntax
AND <Rd>, <Rm>
where:
<Rd> Specifies the register containing the first operand, and is also the destination register.
<Rm> Specifies the register containing the second operand.
Architecture version

All T variants
Exceptions
None
Operation
Rd = Rd AND Rm
N Flag = Rd[31]
Z Flag = if Rd == 0 then 1 else 0
C Flag = unaffected
V Flag = unaffected
Equivalent ARM syntax and encoding
ANDS <Rd>, <Rd>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0100000000 Rm Rd
31302928272625242322212019 1615 1211109876543 0
111000000001 Rd Rd 00000000 Rm
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Thumb Instructions
A7-14
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.11 ASR (1)
This form of the ASR (Arithmetic Shift Right) instruction is used to provide the signed value of a register
divided by a constant power of 2. The condition code flags are updated, based on the result.
Syntax
ASR <Rd>, <Rm>, #<immed_5>
where:
<Rd> Is the destination register for the completed operation.
<Rm> Specifies the register that contains the value to be shifted.
<immed_5> Specifies the shift amount, in the range 1 to 32. Shifts by 1 to 31 are encoded directly
in immed_5. A shift by 32 is encoded as immed_5 == 0.

Architecture version
All T variants
Exceptions
None
Operation
if immed_5 == 0
C Flag = Rm[31]
if Rm[31] == 0 then
Rd = 0
else /* Rm[31] == 1 */]
Rd = 0xFFFFFFFF
else /* immed_5 > 0 */
C Flag = Rm[immed_5 - 1]
Rd = Rm Arithmetic_Shift_Right immed_5
N Flag = Rd[31]
Z Flag = if Rd == 0 then 1 else 0
V Flag = unaffected
15 14 13 12 11 10 6 5 3 2 0
00010 immed_5 Rm Rd
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-15
Equivalent ARM syntax and encoding
MOVS <Rd>, <Rm>, ASR #<immed_5>
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 7 6 5 4 3 0
111000011011 SBZ Rd immed_5 100 Rm
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Thumb Instructions

A7-16
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.12 ASR (2)
This form of ASR is used to provide the signed value of a register divided by a variable power of 2. The
condition code flags are updated, based on the result.
Syntax
ASR <Rd>, <Rs>
where:
<Rd> Contains the value to be shifted, and is also the destination register for the completed
operation.
<Rs> Specifies the register that contains the value of the shift.
Architecture version
All T variants
Exceptions
None
Operation
if Rs[7:0] == 0 then
C Flag = unaffected
Rd = unaffected
else if Rs[7:0] < 32 then
C Flag = Rd[Rs[7:0] - 1]
Rd = Rd Arithmetic_Shift_Right Rs[7:0]
else /* Rs[7:0] >= 32 */
C Flag = Rd[31]
if Rd[31] == 0 then
Rd = 0
else /* Rd[31] == 1 */
Rd = 0xFFFFFFFF
N Flag = Rd[31]

Z Flag = if Rd == 0 then 1 else 0
V Flag = unaffected
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0100000100 Rs Rd
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-17
Equivalent ARM syntax and encoding
MOVS <Rd>, <Rd>, ASR <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 6 5 4 3 0
111000011011 SBZ Rd Rs 0101 Rd
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Thumb Instructions
A7-18
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.13 B (1)
This form of the B (Branch) instruction provides a conditional branch to a target address.
Syntax
B<cond> <target_address>
where:
<cond> Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5.
<target_address>
Specifies the address to branch to. The branch target address is calculated by:
1. Shifting the 8-bit signed offset field of the instruction left by one bit.
2. Sign-extending the result to 32 bits.
3. Adding this to the contents of the PC (which contains the address of the branch

instruction plus 4).
The instruction can therefore specify a branch of approximately ±256 bytes.
Architecture version
All T variants
Exceptions
None
Operation
if ConditionPassed(cond) then
PC = PC + (SignExtend(signed_immed_8) << 1)
15 14 13 12 11 8 7 0
1 1 0 1 cond signed_immed_8
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-19
Usage
To calculate the correct value of signed_immed_8, the assembler (or other toolkit component) needs to:
1. Form the base address for the branch. This is the address of the branch instruction, plus 4. In other
words, the base address is equal to the PC value read by that instruction.
2. Subtract the base address from the target address to form a byte offset. This offset is always even,
because all Thumb instructions are halfword-aligned.
3. If the byte offset is outside the range -256 to +254, use an alternative code-generation strategy or
produce an error as appropriate.
4. Otherwise, set the signed_immed_8 field of the instruction to the byte offset divided by 2.
Notes
Memory bounds Branching backwards past location zero and forwards over the end of the 32-bit
address space is
UNPREDICTABLE.
AL condition If the condition field indicates AL (0b1110), the instruction is instead

UNDEFINED.
When an unconditional branch is required, use the unconditional Branch instruction
described in B (2) on page A7-20.
NV condition If the condition field indicates NV (0b1111), the instruction is a SWI instead (see
SWI on page A7-102).
Equivalent ARM syntax and encoding
A close equivalent is:
B<cond> <target_address>
This differs from the Thumb instruction, because the offset in the ARM instruction is shifted left by 2 before
being added to the PC, whereas the offset in the Thumb instruction is shifted left by 1. Also, the PC values
read by the ARM and Thumb instructions are different.
31 28 27 26 25 24 23 8 7 0
cond 1 0 1 0 sign extension of signed_immed_8 signed_immed_8
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Thumb Instructions
A7-20
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
7.1.14 B (2)
This form of B provides an unconditional branch to a target address.
Syntax
B <target_address>
where:
<target_address>
Specifies the address to branch to. The branch target address is calculated by:
1. Shifting the 11-bit signed offset of the instruction left one bit.
2. Sign-extending the result to 32 bits.
3. Adding this to the contents of the PC (which contains the address of the branch
instruction plus 4).
The instruction can therefore specify a branch of approximately ±2048 bytes.

Architecture version
All T variants
Exceptions
None
Operation
PC = PC + (SignExtend(signed_immed_11) << 1)
Usage
To calculate the correct value of signed_immed_11, the assembler (or other toolkit component) needs to:
1. Form the base address for the branch. This is the address of the branch instruction, plus 4. In other
words, the base address is equal to the PC value read by that instruction.
2. Subtract the base address from the target address to form a byte offset. This offset is always even,
because all Thumb instructions are halfword-aligned.
3. If the byte offset is outside the range -2048 to +2046, use an alternative code-generation strategy or
produce an error as appropriate.
4. Otherwise, set the signed_immed_11 field of the instruction to the byte offset divided by 2.
15 14 13 12 11 10 0
1 1 1 0 0 signed_immed_11
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Thumb Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A7-21
Notes
Memory bounds Branching backwards past location zero and forwards over the end of the 32-bit
address space is
UNPREDICTABLE.
Equivalent ARM syntax and encoding
A close equivalent is:
B <target_address>
This differs from the Thumb instruction, because the offset in the ARM instruction is shifted left by 2 before

being added to the PC, whereas the offset in the Thumb instruction is shifted left by 1. Also, the PC values
read by the ARM and Thumb instructions are different.
31 28 27 26 25 24 23 11 10 0
11101010 sign extension of signed_immed_11 signed_immed_11
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