© 2002 by CRC Press LLC


© 2002 by CRC Press LLC



www.crcpress.com


Fernanda
por tu orgullo
coraje y dignidad
de una mujer luchadora

© 2002 by CRC Press LLC


Preface

Purpose and Background
Computer engineering is such a vast field that it is difficult and almost impossible to present everything
in a single book. This problem is also exaggerated by the fact that the field of computers and computer
design has been changing so rapidly that by the time this book is introduced some of the issues may
already be obsolete. However, we have tried to capture what is fundamental and therefore will be of
lasting value. Also, we tried to capture the trends, new directions, and new developments. This book
could easily fill thousands of pages because there are so many issues in computer design and so many
new fields that are popping out daily. We hope that in the future CRC Press will come with new editions
covering some of the more specialized topics in more details. Given that, and many other limitations, we
are aware that some areas were not given sufficient attention and some others were not covered at all.
However, we hope that the areas covered are covered very well given that they are written by specialists

that are recognized as leading experts in their fields. We are thankful for their valuable time and effort.

Organization
This book contains a dozen sections. First, we start with the fabrication and technology that has been a
driving factor for the electronic industry. No sector of the industry has experienced such tremendous
growth. The progress has surpassed what we thought to be possible, and limits that were once thought
of as fundamental were broken several times. When the first 256 kbit DRAM chips were introduced the
“alpha particle scare” (the problem encountered with alpha particles discharging the memory cell)
predicted that radiation effects would limit further scaling in dimensions of memory chips. Twenty years
later, we have reached 256 Mbit DRAM chips—a thousand times improvement in density—and we see
no limit to further scaling. In fact, the memory capacity has been tripling every two years while the
number of transistors on the processor chip has been doubling every two years.
The next section deals with computer architecture and computer system organization, a top-level view.
Several architectural concepts and organizations of computer systems are described. The section ends
with description of performance evaluation measures, which are the bottom line from the user’s point
of view.
Important design techniques are described in two separate sections, one of which deals exclusively with
power consumed by the system. Power consumption is becoming the most important issue as computers
are starting to penetrate large consumer product markets, and in several cases low-power consumption is
more important than the performance that the system can deliver.
Penetration of computer systems into the consumer’s market is described in the sections dealing with
signal processing, embedded applications, and future directions in computing.
Finally, reliability and testability of computer systems is described in the last section.

© 2002 by CRC Press LLC


Locating Your Topic
Several avenues are available to access desired information. A complete table of contents is presented at
the front of the book. Each of the sections is preceded with an individual table of contents. Finally, each

chapter begins with its own table of contents. Each contributed article contains comprehensive references.
Some of them contain a “To Probe Further” section where a general discussion of various sources such
as books, journals, magazines, and periodicals are discussed. To be in tune with the modern times, some
of the authors have also included Web pointers to valuable resources and information. We hope our
readers will find this to be appropriate and of much use.
A subject index has been compiled to provide a means of accessing information. It can also be used
to locate definitions. The page on which the definition appears for each key defining term is given in the
index.
The Computer Engineering Handbook is designed to provide answers to most inquiries and to direct
inquirers to further sources and references. We trust that it will meet the needs of our readership.

Acknowledgments
The value of this book is completely based on the work of many experts and their excellent contributions.
I am grateful to them. They spent hours of their valuable time without any compensation and with a
sole motivation to provide learning material and help enhance the profession. I would like to thank Prof.
Saburo Muroga, who provided editorial advice, reviewed the content of the book, made numerous
suggestions, and encouraged me to do it. I am indebted to him as well as to other members of the advisory
board. I would like to thank my colleague and friend Prof. Richard Dorf for asking me to edit this book
and trusting me with this project. Kristen Maus worked tirelessly to put all of this material in a decent
shape and so did Nora Konopka of CRC Press. My son, Stanisha, helped me with my English. It is their
work that made this book.

© 2002 by CRC Press LLC


Editor-in-Chief

Vojin G. Oklobdzija is a Fellow of the Institute of Electrical and
Electronics Engineers and Distinguished Lecturer of IEEE SolidState Circuits and IEEE Circuits and Systems Societies. He received
his Ph.D. and M.Sc. degrees from the University of California, Los

Angeles in 1978 and 1982, as well as a Dipl. Ing. (MScEE) from
the Electrical Engineering Department, University of Belgrade,
Yugoslavia in 1971.
From 1982 to 1991 he was at the IBM T. J. Watson Research
Center in New York where he made contributions to the development of RISC architecture and processors. In the course of this work
he obtained a patent on Register-Renaming, which enabled an entire
new generation of super-scalar processors.
From 1988–90 he was a visiting faculty at the University of
California, Berkeley, while on leave from IBM. Since 1991, Prof.
Oklobdzija has held various consulting positions. He was a consultant to Sun Microsystems Laboratories, AT&T Bell Laboratories,
Hitachi Research Laboratories, Silicon Systems/Texas Instruments Inc., and Siemens Corp. where he was
principal architect of the Siemens/Infineon’s TriCore processor. Currently he serves as an advisor to SONY
and Fujitsu Laboratories.
In 1988 he started Integration, which was incorporated in 1996. Integration Corp. delivered several
successful processor and encryption processor designs. (see: www.integration-corp.com)
Prof. Oklobdzija has held various academic appointments, besides the current one at the University
of California. In 1991, as a Fulbright professor, he was helping to develop programs at universities in
South America. From 1996–98 he taught courses in the Silicon Valley through the University of California,
Berkeley Extension, and at Hewlett-Packard.
He holds seven US, four European, one Japanese, and one Taiwanese patents in the area of computer
design and seven others currently pending.
Prof. Oklobdzija is a member of the American Association for Advancement of Science, and the
American Association of the University Professors. He serves on the editorial boards of the IEEE Transaction of VLSI Systems and the Journal of VLSI Signal Processing. He served on the program committees
of the International Conference on Computer Design, the International Symposium on VLSI Technology
and Symposium on Computer Arithmetic. In 1997, he was a General Chair of the 13th Symposium on
Computer Arithmetic and is serving as a program committee member of the International Solid-State
Circuits Conference (ISSCC) since 1996. He has published over 120 papers in the areas of circuits and
technology, computer arithmetic and computer architecture, and has given over 100 invited talks and
short courses in the USA, Europe, Latin America, Australia, China, and Japan.


© 2002 by CRC Press LLC


Editorial Board

Krste Asanovic

Kevin Nowka

Massachusetts Institute of Technology
Cambridge, Massachusetts

IBM Austin Research Laboratory
Austin, Texas

William Bowhill

Takayasu Sakurai

Compaq/DEC
Shrewsbury, Massachusetts

Tokyo University
Tokyo, Japan

Anantha Chandrakasan

Alan Smith

Massachusetts Institute of Technology

Cambridge, Massachusetts

University of California, Berkeley
Berkeley, California

Hiroshi Iwai

Ian Young

Tokyo Institute of Technology
Yokohama, Japan

Intel Corporation
Hillsboro, Oregon

Saburo Muroga
University of Illinois
Urbana, Illinois

© 2002 by CRC Press LLC


© 2002 by CRC Press LLC


© 2002 by CRC Press LLC


© 2002 by CRC Press LLC



© 2002 by CRC Press LLC


Contents

SECTION I Fabrication and Technology

1
2

Trends and Projections for the Future of Scaling and Future
Integration Trends Hiroshi Iwai and Shun-ichiro Ohmi
CMOS Circuits
2.1
2.2
2.3
2.4

VLSI Circuits Eugene John
Pass-Transistor CMOS Circuits Shunzo Yamashita
Synthesis of CMOS Pass-Transistor Logic Dejan Markovi´c
Silicon on Insulator (SOI) Yuichi Kado

3

High-Speed, Low-Power Emitter Coupled Logic
Circuits Tadahiro Kuroda

4


Price-Performance of Computer Technology

SECTION II

5

Computer Systems and Architecture

Computer Architecture and Design
5.1
5.2
5.3
5.4
5.5
5.6

6

John C. McCallum

Server Computer Architecture Siamack Haghighi
Very Large Instruction Word Architectures Binu Mathew
Vector Processing Krste Asanovic
Multithreading, Multiprocessing Manoj Franklin
Survey of Parallel Systems Donna Quammen
Virtual Memory Systems and TLB Structures Bruce Jacob

System Design
6.1

6.2
6.3
6.4

Superscalar Processors Mark Smotherman
Register Renaming Techniques Dezsö Sima
Predicting Branches in Computer Programs Kevin Skadron
Network Processor Architecture Tzi-cker Chiueh

© 2002 by CRC Press LLC


7
8

Architectures for Low Power
Performance Evaluation
8.1
8.2
8.3

9

Measurement and Modeling of Disk Subsystem Performance Jozo J. Dujmovic,´
Daniel Tomasevich, and Ming Au-Yeung
Performance Evaluation: Techniques, Tools,
and Benchmarks Lizy Kurian John
Trace Caching and Trace Processors Eric Rotenberg

Computer Arithmetic

9.1
9.2

High-Speed Computer Arithmetic Earl E. Swartzlander, Jr.
Fast Adders and Multipliers Gensuke Goto

SECTION III

10

Pradip Bose

Design Techniques

Timing and Clocking
10.1 Design of High-Speed CMOS PLLs and DLLs John George Maneatis
10.2 Latches and Flip-Flops Fabian Klass
10.3 High-Performance Embedded SRAM Cyrus (Morteza) Afghahi

11

Multiple-Valued Logic Circuits

12

FPGAs for Rapid Prototyping

13

Issues in High-Frequency Processor Design


K. Wayne Current
James O. Hamblen
Kevin J. Nowka

SECTION IV Design for Low Power

14

Low-Power Design Issues Hemmige Varadarajan, Vivek Tiwari,
Rakesh Patel, Hema Ramamurthy, Shahram Jamshidi,
Snehal Jariwala, and Wenjie Jiang

15

Low-Power Circuit Technologies

16

Techniques for Leakage Power Reduction Vivek De,
Ali Keshavarzi, Siva Narendra, Dinesh Somasekhar,
Shekhar Borkar, James Kao, Raj Nair, and Yibin Ye

© 2002 by CRC Press LLC

Masayuki Miyazaki


17


Dynamic Voltage Scaling

18

Low-Power Design of Systems on Chip

19

Implementation-Level Impact on Low-Power
Design Katsunori Seno

20

Accurate Power Estimation of Combinational CMOS
Digital Circuits Hendrawan Soeleman and Kaushik Roy

21

Clock-Powered CMOS for Energy-Efficient
Computing Nestoras Tzartzanis and William Athas

Thomas D. Burd
Christian Piguet

SECTION V Embedded Applications

22

Embedded Systems-on-Chips


23

Embedded Processor Applications

Wayne Wolf
Jonathan W. Valvano

SECTION VI Signal Processing

24

Digital Signal Processing

25

DSP Applications

26

Digital Filter Design
James H. McClellan

27

Audio Signal Processing

Adam Dabrowski and Tomasz Marciniak

28


Digital Video Processing

Todd R. Reed

29

Low-Power Digital Signal Processing

© 2002 by CRC Press LLC

Fred J. Taylor

Daniel Martin
Worayot Lertniphonphun and

Thucydides Xanthopoulos


SECTION VII Communications and Networks

30

Communications and Computer Networks

SECTION VIII

Anna Ha´c

Input/Output


31

Circuits for High-Performance I/O

32

Algorithms and Data Structures in External
Memory Jeffrey Scott Vitter

33

Parallel I/O Systems

34

A Read Channel for Magnetic Recording

Chik-Kong Ken Yang

Peter J. Varman

34.1 Recording Physics and Organization of Data on a Disk Bane Vasi´c
and Miroslav Despotovi´c
34.2 Read Channel Architecture Bane Vasi´c, Pervez M. Aziz, and Necip Sayiner
34.3 Adaptive Equalization and Timing Recovery Pervez M. Aziz
34.4 Head Position Sensing in Disk Drives Ara Patapoutian
∨
34.5 Modulation Codes for Storage Systems Brian Marcus
and Emina Soljanin
∨

34.6 Data Detection Miroslav Despotovi´c and Vojin Senk
34.7 An Introduction to Error-Correcting Codes Mario Blaum

SECTION IX Operating System

35

Distributed Operating Systems

SECTION X

Peter Reiher

New Directions in Computing

36

SPS: A Strategically Programmable System M. Sarrafzadeh,
E. Bozorgzadeh, R. Kastner, and S. O. Memik

37

Reconfigurable Processors
37.1 Reconfigurable Computing John Morris
37.2 Using Configurable Computing Systems Danny Newport and Don Bouldin

© 2002 by CRC Press LLC


37.3 Xtensa: A Configurable and Extensible Processor Ricardo E. Gonzalez

and Albert Wang

38

Roles of Software Technology in Intelligent
Transportation Systems Shoichi Washino

39

Media Signal Processing
39.1 Instruction Set Architecture for Multimedia
Signal Processing Ruby Lee
39.2 DSP Platform Architecture for SoC Products Gerald G. Pechanek
39.3 Digital Audio Processors for Personal
Computer Systems Thomas C. Savell
39.4 Modern Approximation Iterative Algorithms and Their
Applications in Computer Engineering Sadiq M. Sait
and Habib Youssef

40

Internet Architectures

41

Microelectronics for Home Entertainment

42

Mobile and Wireless Computing


Borko Furht
Yoshiaki Hagiwara

42.1 Bluetooth—A Cable Replacement and More John F. Alexander
and Raymond Barrett
42.2 Signal Processing ASIC Requirements for High-Speed Wireless Data
Communications Babak Daneshrad
42.3 Communication System-on-a-Chip Samiha Mourad and Garret Okamoto
42.4 Communications and Computer Networks Mohammad Ilyas
42.5 Video over Mobile Networks Abdul H. Sadka
42.6 Pen-Based User Interfaces—An Applications Overview Giovanni Seni
and Jayashree Subrahmonia
42.7 What Makes a Programmable DSP Processor Special? Ingrid Verbauwhede

43

Data Security

Matt Franklin

SECTION XI Testing and Design for Testability

44

System-on-Chip (SoC) Testing: Current Practices and Challenges
for Tomorrow R. Chandramouli

© 2002 by CRC Press LLC



45

Testing of Synchronous Sequential Digital Circuits
Z. Stamenkovi´c, and H. T. Vierhaus

46

Scan Testing

47

Computer-Aided Analysis and Forecast of Integrated
Circuit Yield Z. Stamenkovi´c and N. Stojadinovi´c

© 2002 by CRC Press LLC

U. Glaeser,

Chouki Aktouf


I
Fabrication and
Technology
1 Trends and Projections for the Future of Scaling and Future Integration
Trends Hiroshi Iwai and Shun-ichiro Ohmi

Introduction • Downsizing below 0.1 àm ã Gate Insulator ã Gate Electrode ã Source
and Drain • Channel Doping • Interconnects • Memory Technology • Future Prospects


2 CMOS Circuits Eugene John, Shunzo Yamashita,
Dejan Markovi´c, and Yuichi Kado
VLSI Circuits • Pass-Transistor CMOS Circuits • Synthesis of CMOS
Pass-Transistor Logic • Silicon on Insulator (SOI)

3 High-Speed, Low-Power Emitter Coupled Logic Circuits Tadahiro Kuroda
Active Pull-Down ECL Circuits • Low-Voltage ECL Circuits

4 Price-Performance of Computer Technology

John C. McCallum

Introduction • Computer and Integrated Circuit Technology • Processors • Memory
and Storage—The Memory Hierarchy ã Computer SystemsSmall to Large ã Summary

â 2002 by CRC Press LLC


1
Trends and Projections
for the Future of Scaling
and Future Integration
Trends

Hiroshi Iwai
Tokyo Institute of Technology

Shun-ichiro Ohmi
Tokyo Institute of Technology


1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9

Introduction
Downsizing below 0.1 µm
Gate Insulator
Gate Electrode
Source and Drain
Channel Doping
Interconnects
Memory Technology
Future Prospects

1.1 Introduction
Recently, information technology (IT)—such as Internet, i-mode, cellular phone, and car navigation—
has spread very rapidly all over of the world. IT is expected to dramatically raise the efficiency of our
society and greatly improve the quality of our life. It should be noted that the progress of IT entirely
owes to that of semiconductor technology, especially Silicon LSIs (Large Scale Integrated Circuits). Silicon
LSIs provide us high speed/frequency operation of tremendously many functions with low cost, low
power, small size, small weight, and high reliability. In these 30 years, the gate length of the metal oxide
semiconductor field effect transistors (MOSFETs) has reduced 100 times, the density of DRAM increased
500,000 times, and clock frequency of MPU increased 2,500 times, as shown in Table 1.1. Without such

a marvelous progress of LSI technologies, today’s great success in information technology would not be
realized at all.
The origin of the concept for solid-state circuit can be traced back to the beginning of last century, as
shown in Fig. 1.1. It was more than 70 years ago, when J. Lilienfeld using Al/Al2O3/Cu2S as an MOS
structure invented a concept of MOSFETs. Then, 54 years ago, first transistor (bipolar) was realized using
germanium. In 1960, 2 years after the invention of integrated circuits (IC), the first MOSFET was realized
by using the Si substrate and SiO2 gate insulator [1]. Since then Si and SiO2 became the key materials
for electronic circuits. It takes, however, more than several years until the Silicon MOSFET evolved to
Silicon ICs and further grew up to Silicon LSIs. The Silicon LSIs became popular in the market from the
beginning of 1970s as a 1 kbit DRAM and a 4 bit MPU (microprocessor). In the early 1970s, LSIs started

© 2002 by CRC Press LLC


TABLE 1.1
Year

Past and Current Status of Advanced LSI Products
Min.
Lg (µm)

Ratio

DRAM

Ratio

MPU

10

0.1

1
1/100

1k
512 M

1
256,000

750 k
1.7 G

1970/72
2001

Year 2001
20th C

FIGURE 1.1

Ratio
1
2,300

New Century for Solid-State Circuit

73 years since the concept of MOSFET
1928, J. Lilienfeld, MOSFET patent

54 years since the 1st Transistor
1947, J. Bardeen, W. Bratten, bipolar Tr
43-42 years since the 1st Integrated Circuits
1958, J. Kilby, IC
1959, R. Noice, Planar Technolgy
41 years since the 1st Si-MOSFET
1960, D. Kahng, Si-MOSFET
38 years since the 1st CMOS
1963, CMOS, by F. Wanlass, C. T. Sah
31 years since the 1st 1 kbit DRAM (or LSI)
1970 Intel 1103
16 years since CMOS became the major technology
1985, Toshiba 1 Mbit CMOS DRAM

History of LSI in 20th century.

by using PMOS technology in which threshold voltage control was easier, but soon the PMOS was replaced
by NMOS, which was suitable for high speed operation. It was the middle of 1980s when CMOS became
the main stream of Silicon LSI technology because of its capability for low power consumption. Now
CMOS technology has realized 512 Mbit DRAMs and 1.7 GHz clock MPUs, and the gate length of
MOSFETs in such LSIs becomes as small as 100 nm.
Figure 1.2 shows the cross sections of NMOS LSIs in the early 1970s and those of present CMOS LSIs.
The old NMOS LSI technology contains only several film layers made of Si, SiO2, and Al, which are
basically composed of only five elements: Si, O, Al, B, and P. Now, the structure becomes very complicated,
and so many layers and so many elements have been involved.
In the past 30 years, transistors have been miniaturized significantly. Thanks to the miniaturization,
the number of components and performance of LSIs have increased significantly. Figures 1.3 and 1.4
show the microphotographs of 1 kbit and 256 Mbit DRAM chips, respectively. Individual tiny rectangle
units barely recognized in the 16 large rectangle units of the 256 M DRAM correspond to 64 kbit
DRAM. It can be said that the downsizing of the components has driven the tremendous development

of LSIs.
Figure 1.5 shows the past and future trends of the downsizing of MOSFET’s parameters and LSI chip
properties mainly used for high performance MPUs. Future trend was taken from ITRS’99 (International
Technology Roadmap for Semiconductors) [2]. In order to maintain the continuous progress of LSIs for
future, every parameter has to be shrunk continuously with almost the same rate as before. However, it
was anticipated that shrinking the parameters beyond the 0.1 µm generation would face severe difficulties
due to various kinds of expected limitations. It was expected that huge effort would be required in research
and development level in order to overcome the difficulties.
In this chapter, silicon technology from past to future is reviewed for advanced CMOS LSIs.

© 2002 by CRC Press LLC


(a)

6 µm NMOS LSI in 1974

Passivation (PSG)
Al interconnects
ILD (Interlayer
Dielectrics)
(SiO2 + BPSG)

Si
Sisubstrate
substrate

Field SiO2

magnification

Poly Si gate
electrode
Gate SiO2

Source
/ Drain
Source
/ Drain

Layers

Materials
Si, SiO2
Si substrate
BPSG
Field oxide
PSG
Gate oxide
Al
Poly Si gate electrode
Atoms
Source/Drain diffusion
Si, O, Al,
Interlayer dielectrics
P, B
Aluminum interconnects
(H, N, CI)
Passivation

(b) 0.1 µ m CMOS LSI in 2001

Large number of layers,
Many kinds of
materials and atoms
magnification

W via plug
Low k ILD
W contact plug
magnification
CoSi2
Ultra-thin gate SiO2
magnification

FIGURE 1.2

Cross-sections of (a) NMOS LSI in 1974 and (b) CMOS LSI in 2001.

FIGURE 1.3

1 kbit DRAM (TOSHIBA).

© 2002 by CRC Press LLC


FIGURE 1.4

256 Mbit DRAM (TOSHIBA).

ITRS Roadmap
(at introduction)


102
(a)
101

Minimum logic Vdd (V)

MP
UL

100
10−1
10−2
10−3

g

X (µ
j
m)

(µm
)

DR
AM
1/2
pitc
h (µ
m)


Id (mA/µm)

To

x equ

ivale
nt (µ

m)

Wave length of electron (µm)
Tunneling limit in SiO2 (µ m)
Bond length of Si atoms (Physical limit) ( µm)

10−4
1970

1980 1990 2000 2010 2020
Year
ITRS Roadmap
(at introduction)

101
10−1

DRAM chip size (mm2)
2 ?j
imm

e?
siz
ip
h
Uc
MP
ca
pa
cit
y?
iM
bi
ts
?j

103

(b)

MPU maximum
current ?imA)
MPU clock frequency (MHz)

MPU
MPUchip
chipsize
size?imm
mm
i 2 2j?j
MPU power (W)


ors
ist
ns
tra
PU
Hz)
f M ?j
y (T
r o ors
enc
be sist
equ
fr
m
n
k
Nu tra
cloc
cal
?iM
U lo
MP

S
IP
M

DR
AM


105

10−3
1970 1980 1990 2000 2010 2020
Year

FIGURE 1.5

Trends of CPU and DRAM parameters.

© 2002 by CRC Press LLC


1.2 Downsizing below 0.1 µm
In digital circuit applications, a MOSFET functions as a switch. Thus, complete cut-off of leakage current
in the “off ” state, and low resistance or high current drive in the “on” state are required. In addition,
small capacitances are required for the switch to rapidly turn on and off. When making the gate length
small, even in the “off ” state, the space charge region near the drain—the high potential region near the
drain—touches the source in a deeper place where the gate bias cannot control the potential, resulting
in a leakage current from source to drain via the space charge region, as shown in Fig. 1.6. This is the
well-known, short-channel effect of MOSFETs. The short-channel effect is often measured as the threshold
voltage reduction of MOSFETs when it is not severe. In order for a MOSFET to work as a component
of an LSI, the capability of switching-off or the suppression of the short-channel effects is the first priority
in the designing of the MOSFETs. In other words, the suppression of the short-channel effects limits the
downsizing of MOSFETs.
In the “on” state, reduction of the gate length is desirable because it decreases the channel resistance
of MOSFETs. However, when the channel resistance becomes as small as source and drain resistance,
further improvement in the drain current or the MOSFET performance cannot be expected. Moreover,
in the short-channel MOSFET design, the source and drain resistance often tends to even increase in

order to suppress the short-channel effects. Thus, it is important to consider ways for reducing the total
resistance of MOSFETs with keeping the suppression of the short-channel effects. The capacitances of
MOSFETs usually decreases with the downsizing, but care should be taken when the fringing portion
is dominant or when impurity concentration of the substrate is large in the short-channel transistor
design.
Thus, the suppression of the short-channel effects, with the improvement of the total resistance and
capacitances, are required for the MOSFET downsizing. In other words, without the improvements of
the MOSFET performance, the downsizing becomes almost meaningless even if the short-channel effect
is completely suppressed.
To suppress the short-channel effects and thus to secure good switching-off characteristics of MOSFETs,
the scaling method was proposed by Dennard et al. [3], where the parameters of MOSFETs are shrunk
or increased by the same factor K, as shown in Figs. 1.7 and 1.8, resulting in the reduction of the space
charge region by the same factor K and suppression of the short-channel effects.
2
In the scaling method, drain current, Id (= W/L × V /tox), is reduced to 1/K. Even the drain current is
reduced to 1/K, the propagation delay time of the circuit reduces to 1/K, because the gate charge reduces
2
to 1/K . Thus, scaling is advantageous for high-speed operation of LSI circuits.
2
If the increase in the number of transistors is kept at K , the power consumption of the LSI—which
2
is calculated as 1/2fnCV as shown in Fig. 1.7—stays constant and does not increase with the scaling.
Thus, in the ideal scaling, power increase will not occur.
0 V

Vdd (V)

0 V
Gate
Source


Leakage Current
Space Charge
Region

FIGURE 1.6

Short channel effect at downsizing.

© 2002 by CRC Press LLC

Drain