551

Digital Logic Testing and Simulation

,

Second Edition

, by Alexander Miczo
ISBN 0-471-43995-9 Copyright © 2003 John Wiley & Sons, Inc.

CHAPTER 11

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11.1 INTRODUCTION

Test strategies described in previous chapters relied on two concepts: controllability
and observability (C/O). Good controllability makes it easier to drive a circuit into a
desired state, thus making it easier to sensitize a targeted fault. Good observability
makes it easier to monitor the effects of a fault. Solutions for solving C/O problems
include scan path and various ad-hoc methods. Scan path reduces C/O to a combina-
tional logic problem which, as explained in Chapter 4, is a solved problem (theoreti-
cally, at least).

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monitoring is another approach that provides complete observability. Current
drain in a properly functioning, fully static CMOS IC is negligible when the clock is
inactive. However, when the IC is defective, due to the presence of leakage in the cir-
cuit, or possibly even to an open, current flow usually becomes excessive. This rise in
current flow can be detected by monitoring the current supplied by the tester. How
effective is this technique for spotting defective ICs? In one study, it was shown that

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testing with a test program that provided 60% coverage of stuck-at faults pro-
vided the same AQL as a test program with 90% stuck-at coverage without

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.

1

The stuck-at fault model that we have been dealing with up to this point is not
intended to address qualitative issues; its primary target is solid defects manifested as
signals stuck-at logic 1 or logic 0. An IC may run perfectly well on a tester operating at
1 or 2 MHz, at room temperature, but fail in the system. Worse still, an IC may fail
shortly after the product is delivered to the customer. This is often due to leakage paths
that degrade to catastrophic failure mode shortly after the product is put into service.

11.2 BACKGROUND


The CMOS circuit was patented in 1963 by Frank Wanlass.

2

His two-transistor
inverter consumed just a few nanowatts of standby power, whereas equivalent
bipolar circuits of the time consumed milliwatts of power in standby mode. During

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the 1970s, companies began measuring leakage of CMOS parts to identify those that
had excessive power consumption.

3

At times it was a useful adjunct to the traditional
functional testing for stuck-at faults, and at other times it was critical to achieve
quality levels required by customers.
The classic stuck-at fault model, while identifying unique signal paths (cf. Sec-
tion 7.5) and providing a means for quantitatively measuring the completeness of a
test for these paths, does not model many of the fault classes that can occur, particu-
larly in deep submicron circuits. In fact, as was pointed out in Section 3.4 that the
stuck-at fault can be thought of as a behavioral model for very low level behavioral
devices, namely, the logic gates.
Faults such as high-resistance bridging shorts, inside a logic gate or between con-

nections to adjacent gates, may not be visible during a functional test. A leakage
path may cause path delay, so the circuit does not operate correctly at speed, but it
may operate correctly if the circuit is tested at a speed much slower than its design
speed, since there may be enough time for a charge to build up and force the gate to
switch. Shorts between signal runs on the die are usually overlooked during func-
tional testing, because, in general, there is no fault model to determine if they have
been tested. If there were fault models for these shorts, perhaps generated by a lay-
out program, the number of these faults would be prohibitively large and would
aggravate a frequently untenable fault simulation problem (cf. Section 3.4).
Excess current detected during test may indicate reliability problems. The
inverter depicted in Figure 11.1 has a short circuit from gate to drain of

Q

1

. In nor-
mal operation, when input

A

switches from 0 to 1, there is a brief rush of current
between

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and ground. Shortly thereafter, a high at the gate of


Q

1

causes a near
complete cutoff of current, the measured flow typically being a few nanoamperes.
This minuscule current flow is quite important in battery operated applications,
ranging from human implants to laptop computers. However, because of the defect,
there is a path from ground, through the drain of

Q

2

, to the source of

Q

1

and then to
the gate. The output

F

in this example will likely respond with the correct value,
since it is logically connected to ground through

Q


2

, but current flow will be exces-
sive, and there is the possibility of a catastrophic failure in the future.
Interestingly, although much attention is given to detection of shorts by

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, it
can also detect open circuits. When an open occurs, it is often the case that neither

Figure 11.1

CMOS inverter.
Short circuit
A
F
A
F
Time
Current
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(defect)
V
DD
V
SS

Q
1
Q
2

SELECTING VECTORS

553

transistor of a transistor pair is completely turned off. As a result, a leakage path
from ground to

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DD

exists. This is significant because, in conventional stuck-fault
testing, a two-vector combination is required to detect stuck-open faults in CMOS
circuits (cf. Section 7.6.2).

11.3 SELECTING VECTORS

In order to measure leakage current, the circuit must be in a fully initialized state.

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measurements must be made on quiet vectors—that is, vectors with very little
leakage current. During simulation, those vectors for which indeterminate values are

detected must immediately be eliminated as candidates for current measurement.
During test, when the circuit reaches a vector at which a current measurement is to
be made, the circuit must be held in a steady state for a sufficient duration to allow
all switching transients to subside. Some design rules include:
No pullups or pulldowns.
No floating nodes.
No logic contention.
If analog circuits appear in the design, they should be on separate power supplies.
No unconnected inputs on unused logic.
The purpose of these design rules is to prevent excess current flows during quies-
cent periods. Pullups and pulldowns provide resistive paths to ground or power. On
average, a node is going to be at logic 0 half the time and at logic 1 half the time. If the
node is at logic 0 and is connected to a pullup, a path exists for current flow. Floating
inputs may stabilize at a voltage level somewhere between ground and

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DD

, thus pro-
viding a current path. Incompletely specified busses can be troublesome. For example,
if a bus has three drivers, a logic designer may design the circuit in such a way that the
select logic floats the bus when no driver is active. Hence, any inputs driven by the bus
will be floating. Bus keeper cells are recommended to prevent floating buses.

1

In general, any circuit configuration that causes a steady current drain from the
power supply runs the risk of masking failure effects, since the effectiveness of


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relies on the ability to distinguish between the very low quiescent current drain for a
defect-free circuit and the high current caused by a defect. Interestingly, redundant
logic, which is troublesome for functional testing, does not adversely affect

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testing. In fact,

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can detect defects in redundant logic that a functional test can-
not detect.

11.3.1 Toggle Count

Toggle count has been used for many years as a metric for evaluating the thorough-
ness of gate-level simulations for design verification. When schematic entry was the
primary medium for developing logic circuits, and the level of abstraction was logic

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gates, toggle count could be used to identify nodes on the schematics that were
never toggled to a particular value. Those nodes were then targeted during simula-
tion, the objective being to get all or nearly all nodes toggled to both 1 and 0.
Since one of the objectives of

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is to identify circuits with short circuits between
signal lines and power or ground, the toggle count can be an effective method for
determining the effectiveness of a given test. If a particular set of test vectors has a
high toggle percentage, meaning that a high percentage of nodes toggled to both 1 and
0, then it is reasonable to expect that a high percentage of shorts will be detected.
The computation is quite straightforward: simply identify the gate that is driving
each line in the circuit and note whether it has toggled to a 1 or 0 at the end of each
vector. Then, during simulation, the first step is to determine whether or not the vec-
tor can be used for

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. Recall that a vector cannot be a candidate if the circuit is
not yet fully initialized, or if there is bus contention. If the vector is a candidate, then
determine how many previously untoggled nodes are toggled by this vector. Since
there is usually a limit on the number of vectors for which the tester can make


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measurements, it is desirable to select vectors such that each vector selected contrib-
utes as many new nodes as possible to the collection of toggled nodes.
The first vector that meets acceptance criteria is generally going to provide about
50% coverage, since every node is at 1 or 0. A scheme described in the Quietest
method (next section), but that is also applicable here, establishes a percentage of the
untoggled node values as an objective. As an example, an objective might be estab-
lished that bars a vector from being selected unless it toggles at least 10% of the
currently untoggled node values. As toggle coverage increases, the 10% selection
criteria remains, but the absolute number of newly toggled node values decreases.
This procedure can be applied iteratively. For example, a given percentage may
be too restrictive; as a result, no new vectors are selected after some toggle coverage
is reached. Those vectors can be retained, and then simulation can be rerun with a
lower percentage threshold, say 5%. This will usually cause additional vectors to be
selected. If the maximum allowable number of vectors has not been reached, and the
toggle coverage has not yet reached an acceptable level, this procedure can again be
repeated with yet another lower selection percentage.

11.3.2 The Quietest Method

The

quietest method

is based on the observation that six shorts can occur in a single
MOS transistor:


4

f

GS

gate and source

f

GD

gate and drain

f

SD

source and drain

f

BS

bulk and source

f

BD


bulk and drain

f

BD

bulk and gate

SELECTING VECTORS

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Figure 11.2

MOS transistor short fault model.

These shorts are seen in Figure 11.2. The approach used in this method is applicable
at the transistor level or at the macrocell level. It begins with a table for a particular
cell, which could be a simple logic gate, or a full-adder, or a considerably more
complex circuit. All input combinations to the cell are fault-simulated at the transis-
tor level. This list of transistor shorts permits

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fault simulation of the entire cir-
cuit to be accomplished hierarchically.
The first step is to simulate each transistor or macrocell and to fault-simulate

each of the faults. A table is created for each cell, listing I/O combinations versus
faults detected (see Figure 11.3). The NAND gate, Figure 11.3(a), is simulated, and
the table of Figure 11.3(b) is constructed. This table is a matrix of dimension

m

×

n

,
where

m

= 2

k

is the number of rows, and

k

is the number of I/O pins. The circuit
shown in Figure 11.3 has two inputs and one output, so there are 2

3

rows.
The number of columns,


n

, corresponds to the number of transistors. Each entry
in the table is a two-character octal number. The six bits corresponds to the six tran-
sistor faults, as defined in Figure 11.3(c). The all-zero row entries for combinational
logic correspond to combinations that cannot occur. For example, row 2 corresponds

Figure 11.3

Lookup table for

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faults.
Gate
Source Drain
Bulk
A
B
X
i
0
1
2
3
4
5

6
7
N1
0
22
0
26
0
70
43
0
N2
0
0
0
43
0
26
43
0
P1
0
43
0
43
0
0
26
0
P2

0
43
0
0
0
43
26
0
f
BG
f
BD
f
BS
f
SD
f
GD
f
GS
(a) (b)
(c)
N1
N2
P1 P2

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to the combination

A, B, X

= (0,1,0), which is inconsistent with the definition of a
NAND gate. Note, however, that some combinations in sequential circuits may rely
on the presence of feedback.
Once the table is created, it can be used to compute

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coverage for the cell
during normal logic simulation. At the end of each vector, the input combination on
each macrocell is examined. If the combination has not been generated by any previ-
ously selected

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vector, then any short faults detected by this combination, and
not previously marked as detected, can be selected and tallied for the current vector.
After all cells have been examined, the incremental improvement in fault coverage
for the vector can be computed. If the vector satisfies some criteria, such as that
described in the previous subsection, it can be accepted and added to the collection
of vectors for which


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measurements are to be made.

11.4 CHOOSING A THRESHOLD

One of the problems associated with

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is choice of a current threshold. Different
devices exhibit different amounts of leakage current. Even different devices of the
same die size may have significantly different amounts of leakage current, depend-
ing on the kind of logic and/or memory that is contained on the die. Furthermore, the
same device, when tested at wafer sort and at package test, will exhibit different
leakage. The target application of the IC will influence the leakage threshold: Manu-
facturers of ICs for portable applications or human implants will have much more
stringent requirements on leakage current.
The issue is further complicated by the fact that different vectors from the same
test vector set can have noticeably different leakage currents. As a result, it is a non-
trivial task to establish a threshold for current. A threshold that is too lax results in
keeping devices that should be discarded. Conversely, a threshold that is too rigor-
ous results in discarding good devices. One source suggests that if

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of the device
under test is greater than 100

µ

A for all vectors under normal conditions, the IC can-
not be tested by means of

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measurement.

5

Determining a threshold starts with a histogram of

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current versus number of
devices that occur in each bin of the histogram. Figure 11.4 shows a histogram for
11,405 microcontrollers.

6


The author uses

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to denote the fact that current is mea-
sured at

V

SS

rather than

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DD

. In an IEEE QTAG (Quality Test Action Group) survey,
respondents were asked where they would set a threshold for the data in
Figure 11.4.

7
The following results were obtained:
500–100 µA3
100–50 µA7
50–25 µA4
25–10 µA3

10–5 µA6
<5 µA5