At Speed Debugging Techniques
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CHAPTER
18
At Speed
Debugging
Techniques
Throughout the book so far we have discussed a number
of techniques for implementing VHDL designs and ways
to make sure that the VHDL designs behave as expected.
These techniques include simulation, synthesis of the
design to an FPGA or ASIC, and gate-level simulation
using VITAL libraries. A new technique called At-Speed
Debugging is just becoming available that allows much
higher performance verification than a typical simulator,
yet provides the design visibility necessary to properly
debug a design. This technique provides designers with
the ability to debug their design in the target system, at
target speed, at the VHDL RTL level.
Figure 18-1 shows a block diagram of how this works.
The VHDL for the device is read into a tool that auto-
matically creates and inserts a small debug core into the
device that probes internal signals. The debug core is cre-
ated based on information from the designer about what
18
signals are to be probed. This debug core communicates through the
JTAG port on the device to an HDL debugger executing on a host plat-
form. The HDL debugger sends and receives data from the debug core
and displays this data in context with the HDL for the design. Wave-
forms of the internal device data can also be displayed, providing the
ability to trace down problems in the design.
This technique works well for any design, but it works especially well
for designs where a tremendous amount of data must be processed by
the device to determine whether the device is working properly. For
instance, devices that process audio or video information require a
tremendous amount of data to be processed before it can be determined
that the device is working properly. A video processor might need to pro-
duce several minutes of high-quality video data to determine whether
the encryption decoding algorithm is working properly. Running at or
near speed will allow images to be generated quickly and the device
function to be analyzed for correctness.
The only system as of this writing that performs as described is the
Bridges2Silicon debugger from Bridges2Silicon. A block diagram of the
system is shown in Figure 18-2.
The Bridges2Silicon debugger contains two tools. The Bridges2Silicon
instrumentor reads the VHDL description and adds the debug core, called
an Intelligent In-Circuit Emulator (IICE) to the design. The Bridges2Silicon
debugger communicates with the JTAG port on the target device, reads
the database created by the instrumentor, and reads the original source
files created by the designer.
Chapter Eighteen
400
FPGA or
SOC
FPGA or
SOC
IICE
JTAG
Hardware System
HDL
Debugger
Figure 18-1
At-Speed Debugging
Overview.
Instrumentor
The designer reads the VHDL design into the instrumentor and specifies
which signals to probe and which breakpoints to enable. The instrumentor
generates a new VHDL description of the design with the IICE core added
and connected to the appropriate places in the design. Once the new VHDL
description has been created, the designer synthesizes, and place and route
the new VHDL description. In an FPGA design environment, the device is
programmed with the new device file created by place and route.
Debugger
Once the board is powered up, and the FPGA device is programmed with
the new device file from place and route, the debugger can communicate
with the device through the JTAG port. The debugger also reads the data-
base file created by the Instrumentor and the original VHDL source files.
The instrumentor database relates the real signals on the device to the
location of the signals in the original HDL.
Debug CPU Design
Let’s now look at the process of debugging the CPU design using the
Bridges2Silicon Debugger. The first step is to create a project containing
all of the HDL files for the design.
401
At Speed Debugging Techniques
HDL
Sources
IICE
Implement
(Synthesis, P&R)
SOC
Implement
(Synthesis, P&R)
Bridges2Silicon
Instrumentor
Instrumented
HDL
Sources
B2S
Project
Bridges2Silicon
Instrumentor
B2S
Project
Bridges2Silicon
Debugger
JTAG
Bridges2Silicon
Debugger
JTAG
Figure 18-2
Bridges2Silicon
Debugger Overview.
Create Project
To create a project, use the project editor invoked from the File
menu or from the toolbar. The Project Editor window is shown in Fig-
ure 18-3.
To add to the project, use the file navigator in the upper left to nav-
igate to the location of files. First select the files and use the right arrow
key to add the files to the Design File list on the right of the project
editor window as shown in Figure 18-4. Now the design source files
need to be re-ordered so that the files are read in the proper order,
which is specified by the order of the list. The package
cpulib.vhd
needs to be read first so that it is available to all the other design files.
The easiest way to move
cpulib.vhd
to the top of the list is to select
and drag it to the top of the list. The other file that needs to be moved
is the top level of the design,
cpu.vhd
. File
cpu.vhd
needs to be moved to
the bottom of the list so that it is the last file read.
Chapter Eighteen
402
Figure 18-3
Bridges2Silicon Project
Editor Window.
403
At Speed Debugging Techniques
Specify Top-Level Parameters
Once all the files have been specified, the parameters for the top level
need to be specified so that the design elements can be properly linked.
There are two parameters that need to be specified: the
TOP-LEVEL UNIT
and
TOP-LEVEL LANGUAGE
.
TOP-LEVEL UNIT
specifies which design unit is
the top level and will be linked. This value will be specified as CPU.
TOP-
LEVEL LANGUAGE
specifies the default language used to compile the design
and to write out the instrumented design.
TOP-LEVEL LANGUAGE
is specified
as VHDL by clicking the VHDL radio button. This is shown in Figure 18-5.
Now that we have specified all the needed parameters, click the OK but-
ton, which saves the project and also compiles the project. After compila-
tion, Figure 18-6 shows the design loaded into the Instrumentor Window.
Specify Project Parameters
Once all the files have been added to the project, the device parame-
ters need to be specified. These parameters determine how the device
Figure 18-4
Files added to Project
File List.
