1. The type/s of packets sent by the USB is/are _______.
a) Control
b) Data
c) Data, Control
d) Address
2. During the execution of the instructions, a copy of the instructions is placed in the
______ .
a) Register
b) RAM
c) System heap
d) Cache
3. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz
respectively. Suppose A can execute an instruction with an average of 3 steps and B
can execute with an average of 5 steps. For the execution of the same instruction
which processor is faster ?
a) A
b) B
C) Both take the same time
d) Insuffient information
4. A processor performing fetch or decoding of different instruction during the
execution of another instruction is called ______ .
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of these
5. When Performing a looping operation, the instruction gets stored in the ______.
a) System Heap
b) Cache.
c) Registers

d) System stack
6. For a given FINITE number of instructions to be executed, which architecture of the
processor provides for a faster execution ?
a) ISA
b) ANSA
c) Super-scalar
d) All of the above
7. The clock rate of the processor can be improved by,
a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using overclocking method
d) All of the above
8. An optimizing Compiler does,
a) Better compilation of the given piece of code.
b) Takes advantage of the type of processor and reduces its process time.
c) Does better memory managament.
d) Both a and c
9. The ultimate goal of a compiler is to,
a) Reduce the clock cycles for a programming task.
b) Reduce the size of the object code.
c) Be versatile.
d) Be able to detect even the smallest of errors.
10. SPEC stands for,
a) Standard Performance Evaluation Code.
b) System Processing Enhancing Code.
c) System Performance Evaluation Corporation.
d) Standard Processing Enhancement Corporation.


11. As of 2000, the reference system to find the performance of a system is _____ .

a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
d) None of these
12. If a system is 64 bit machine , then the length of each word will be ____.
a) 12 bytes
b) 8 bytes
c) 4 bytes
d) 16 bytes
13. 10. When Performing a looping operation, the instruction gets stored in the ______ .
a) Registers
b) Cache
c) System Heap
d) System stack
14. 11. The average number of steps taken to execute the set of instructions can be made
to be less than one by following _______ .
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
15. The flash memory modules designed to replace the functioning of an harddisk is
______.
a) Flash drives
b) DIMM
c) FIMM
d) RIMM
16. If a processor clock is rated as 1250 million cycles per second, then its clock period is
________ .



a) 1.9 * 10 ^ -10 sec
b) 1.6 * 10 ^ -9 sec
c) 1.25 * 10 ^ -10 sec
d) 8 * 10 ^ -10 sec
17. If the instruction, Add R1,R2,R3 is executed in a system which is pipe-lined, then the
value of S is (Where S is term of the Basic performance equation)
a) 3
b) ~2
C) ~1
d) 6
18. CISC stands for,
a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
19. As of 2000, the reference system to find the SPEC rating are built with _____
Processor .
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
20. The smallest entity of memory is called as _______ .
a) Cell
b) Block
c) Instance
d) Unit
21. The collection of the above mentioned entities where data is stored is called as
______ .
a) Block



b) Set
c) Word
d) Byte
22. An 24 bit address generates an address space of ______ locations .
a) 1024
b) 4096
c) 2 ^ 48
d) 16,777,216
23. If a system is 64 bit machine , then the length of each word will be ____ .
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
24. The type of memory assignment used in Intel processors is _____ .
a) Little Endian
b) Big Endian
c) Medium Endian
d) None of the above
25. When using the Big Endian assignment to store a number, the sign bit of the number
is stored in _____ .
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
d) None of the above
26. To get the physical address from the logical address generated by CPU we use ____ .
a) MAR
b) MMU
c) Overlays
d) TLB



27. _____ method is used to map logical addresses of variable length onto physical
memory.
a) Paging
b) Overlays
c) Segmentation
d) Paging with segmentation
28. During transfer of data between the processor and memory we use ______ .
a) Cache
b) TLB
c) Buffers
d) Registers
29. Physical memory is divided into sets of finite size called as ______ .
a) Frames
b) Pages
c) Blocks
d) Vectors
30. The main virtue for using single Bus structure is ,
a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
d) None of these
31. The memory devices which are similar to EEPROM but differ in the cost
effectiveness is ______.
a) CMOS
b) Memory sticks
c) Blue-ray devices
d) Flash memory
32. ______ are used to over come the difference in data transfer speeds of various

devices .


a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
33. To extend the connectivity of the processor bus we use ______ .
a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
34. IBM developed a bus standard for their line of computers ‘PC AT’ called _____ .
a) IB bus
b) M-bus
c) ISA
d) None of these
35. The bus used to connect the monitor to the CPU is ______ .
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
36. ANSI stands for,
a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
37. _____ register Connected to the Processor bus is a single-way transfer capable .
a) PC
b) IR

c) Temp
d) Z


38. In multiple Bus organisation, the registers are collectively placed and referred as
______ .
a) Set registers
b) Register file
c) Register Block
d) Map registers
39. The main advantage of multiple bus organisation over single bus is,
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of these
40. The ISA standard Buses are used to connect,
a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
41. The decoded instruction is stored in ______ .
a) IR
b) PC
c) Registers
d) MDR
42. The instruction -> Add LOCA,R0 does,
a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0


43. Which registers can interact with the secondary storage ?
a) MAR


b) PC
c) IR
d) R0
44. During the execution of a program which gets initialized first ?
a) MDR
b) IR
c) PC
d) MAR
45. Which of the register/s of the processor is/are connected to Memory Bus ?
a) PC
b) MAR
c) IR
d) Both a and b
46. ISP stands for,
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
47. The internal Components of the processor are connected by _______ .
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
48. ______ is used to choose between incrementing the PC or performing ALU
operations .

a) Conditional codes
b) Multiplexer
c) Control unit
d) None of these


49. The registers,ALU and the interconnection between them are collectively called as
_____ .
a) Process route
b) Information trail
c) information path
d) data path
50. _______ is used to store data in registers .
a) D flip flop
b) JK flip flop
c) RS flip flop
d) none of these
51. During the execution of the instructions, a copy of the instructions is placed in the
______ .
a) Register
b) RAM
c) System heap
d) Cache
52. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz
respectively. Suppose A can execute an instruction with an average of 3 steps and B
can execute with an average of 5 steps. For the execution of the same instruction
which processor is faster ?
a) A
b) B
c) Both take the same time

d) Insuffient information

53. A processor performing fetch or decoding of different instruction during the
execution of another instruction is called ______ .
a) Super-scaling


b) Pipe-lining
c) Parallel Computation
d) None of these
54. For a given FINITE number of instructions to be executed, which architecture of the
processor provides for a faster execution ?
a) ISA
b) ANSA
c) Super-scalar
d) All of the above
55. The clock rate of the processor can be improved by,
a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using overclocking method
d) All of the above
56. An optimizing Compiler does,
a) Better compilation of the given piece of code.
b) Takes advantage of the type of processor and reduces its process time.
c) Does better memory managament.
d) Both a and c
57. The ultimate goal of a compiler is to,
a) Reduce the clock cycles for a programming task.
b) Reduce the size of the object code.
c) Be versatile.

d) Be able to detect even the smallest of errors.
58. SPEC stands for,
a) Standard Performance Evaluation Code.
b) System Processing Enhancing Code.
c) System Performance Evaluation Corporation.
d) Standard Processing Enhancement Corporation.


59. As of 2000, the reference system to find the performance of a system is _____ .
a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
d) None of these
60. When Performing a looping operation, the instruction gets stored in the ______ .
a) Registers
b) Cache
c) System Heap
d) System stack
61. The average number of steps taken to execute the set of instructions can be made to
be less than one by following _______ .
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
62. If a processor clock is rated as 1250 million cycles per second, then its clock period is
________ .
a) 1.9 * 10 ^ -10 sec
b) 1.6 * 10 ^ -9 sec
c) 1.25 * 10 ^ -10 sec
d) 8 * 10 ^ -10 sec

63. If the instruction, Add R1,R2,R3 is executed in a system which is pipe-lined, then the
value of S is (Where S is term of the Basic performance equation)
a) 3
b) ~2
c) ~1
d) 6


64. CISC stands for,
a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
65. As of 2000, the reference system to find the SPEC rating are built with _____
Processor .
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
66. The DMA differs from the interrupt mode by
a) The involvement of the processor for the operation
b) The method accessing the I/O devices
c) The amount of data transfer possible
d) Both a and c
67. The DMA transfers are performed by a control circuit called as
a) Device interface
b) DMA controller
c) Data controller
d) Overlooker
68. In DMA transfers, the required signals and addresses are given by the

a) Processor
b) Device drivers
c) DMA controllers
d) The program itself
69. After the complition of the DMA transfer the processor is notified by
a) Acknowledge signal
b) Interrupt signal


c) WMFC signal
d) None of the above
70. The DMA controller has _______ registers
a) 4
b) 2
c) 3
d) 1
71. When the R/W bit of the status register of the DMA controller is set to 1,
a) Read operation is performed
b) Write operation is performed
72. The controller is connected to the ____
a) Processor BUS
b) System BUS
c) External BUS
d) None of the above
73. Can a single DMA controller perform operations on two different disks
simulteneously…??
a) True
b) False
74. The technique where the controller is given complete access to main memory is
a) Cycle stealing

b) Memory stealing
c) Memory Con
d) Burst mode

75. The controller uses _____ to help with the transfers when handling network
interfaces.
a) Input Buffer storage
b) Signal echancers


c) Bridge circuits
d) All of the above
76. To overcome the conflict over the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
d) None of the above
77. The registers of the controller are ______
a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits
78. When process requests for a DMA transfer ,
a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) Both a and c
79. The DMA transfer is initiated by _____
a) Processor
b) The process being executed

c) I/O devices
d) OS
80. If the transistor gate is closed, then the ROM stores a value of 1.
a) True
b) False
81. PROM stands for
a) Programmable Read Only Memory.
b) Pre-fed Read Only Memory.


c) Pre-required Read Only Memory.
d) Programmed Read Only Memory.
82. The PROM is more effective than ROM chips in regard to _______.
a) Cost
b) Memory management
c) Speed of operation
d) Both a and c
83. The serial port is used to connect basically _____ and processor.
a) Printer
b) Speakers
c) Monitor
d) I/O devices
84. The difference between the EPROM and ROM circuitory is _____.
a) The usage of MOSFET’s over transistors.
b) The usage of JFET’s over transistors.
c) The usage of an extra transistor.
d) None of the above.
85. The ROM chips are mainly used to store _______.
a) System files
b) Root directories

c) Boot files
d) Driver files
86. The contents of the EPROM are earsed by
a) Overcharging the chip.
b) Exposing the chip to UV rays.
c) Exposing the chip to IR rays.
d) Discharging the Chip.
87. The disadvantage of the EPROM chip is
a) The high cost factor.


b) The low efficiency.
c) The low speed of operation.
d) The need to remove the chip physically to reprogram it.
88. EEPROM stands for Electrically Erasable Programmable Read Only Memory.
a) True
b) False
89. The disadvantage of the EEPROM is/are
a) The requirement of different voltages to read,write and store information.
b) The Latency inread operation.
c) The inefficient memory mapping schemes used.
d) All of the above.
90. The memory devices which are similar to EEPROM but differ in the cost
effectiveness is ______.
a) Memory sticks
b) Blue-ray devices
c) Flash memory
d) CMOS
91. The only difference between the EEPROM and flash memory is that the latter doesn’t
allow bulk data to be written.

a) True
b) False
92. ANSI stands for
a) ASCII National Standard Interface
b) American Network System Interface
c) American National System Interface
d) American National Standard Institute
93. The flash memories find application in ______.
a) Super computers
b) Mainframe systems


c) Distributed systems
d) Portable devices
94. The memory module obtained by placing a number of flash chips for higher memory
storage called as _______.
a) FIMM
b) SIMM
c) Flash card
d) RIMM
95. The flash memory modules designed to replace the functioning of an harddisk is
______.
a) RIMM
b) Flash drives
c) FIMM
d) DIMM
96. The transfer rate, when the USB is operating in low-speed of operation is _____.
a) 2.5 Mb/s
b) 12 Mb/s
c) 5 Mb/s

d) 1.5 Mb/s
97. The reason for the fast operating speeds of the flash drives is
a) The absence of any movable parts.
b) The itegarated electronic hardware.
c) The improved bandwidth connection.
d) All of the above.
98. The reason for the implementation of the cache memory is
a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
d) All of the above


99. The effectiveness of the cache memory is based on the property of ________.
a) Locality of reference
b) Memory localisation
c) Memory size
d) None of the above
100.

The temporal aspect of the locality of reference means

a) That the recently executed instruction wont be executed soon
b) That the recently executed instruction is temporarily not referenced
c) That the recently executed instruction will be executed soon again
d) None of the above
101.

The spatial aspect of the locality of reference means


a) That the recently executed instruction is executed again next
b) That the recently executed wont be executed again
c) That the instruction executed will be executed at a later time
d) That the instruction in close proximity of the instruction executed will be executed
in future
102.

The correspondence between the main memory blocks and those in the cache is

given by _________.
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
103.

The transfer of large chunks of data with the involvement of the processor is done

by _______.
a) User system programs
b) None of the above
c) DMA controller
d) Arbitrator


104.

The algorithm to remove and place new contents into the cache is called _______.

a) Replacement algorithm

b) Renewal algorithm
c) Updation
d) None of the above
105.

The write-through procedure is used

a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache simultaneously
d) None of the above
106.

The bit used to signify that the cache location is updated is ________.

a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
107.

The registers of the controller are ______.

a) 64 bits
b) 24 bits
c) 16 bits
d) 32 bits
108.

The copy-back protocol is used


a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to the memory
d) None of the above

109.

The approach where the memory contents are transfered directly to the processor

from the memory is called ______.
a) Read-later


b) Read-through
c) Early-start
d) None of the above
110.

The CPU is also called as ________.

a) Processor hub
b) ISP
c) Controller
d) All of the above
111.

A common strategy for performance is making various functional units operate

parallely.

a) True
b) False
112.

The PC gets incremented

a) After the instruction decoding
b) After the IR instruction gets executed
c) After the fetch cycle
d) None of the above
113.

Which register in the processor is single directional ?

a) MAR
b) MDR
c) PC
d) Temp
114.

The BOOT sector files of the system are stored in _____.

a) ROM
b) Fast solid state chips in the motherboard
c) Harddisk
d) RAM
115.

The transparent register/s is/are __________.


a) Y


b) Z
c) Temp
d) All of the above
116.

_ bus structure is usually used to connect I/O devices.

a) Single bus
b) Multiple bus
c) Rambus
d) Star bus
117.

Which register is connected to the MUX ?

a) Y
b) Z
c) R0
d) Temp
118.

The registers,ALU and the interconnecting path together are called as ______.

a) Control path
b) Flow path
c) Data path
d) None of the above

119.

The input and output of the registers are governed by __________.

a) Transistors
b) Diodes
c) Gates
d) Switches
120.

When two or more clock cycles are used to complete data transfer it is called as

________.
a) Single phase clocking
b) Multi-phase clocking
c) Edge triggered clocking
d) None of the above


121.

The serial port is used to connect basically _____ and processor.

a) Printer
b) Speakers
c) Monitor
d) I/O devices
122.

________ signal is used to show complete of memory operation.


a) MFC
b) WMFC
c) CFC
d) None of the above
123.

If the transistor gate is closed, then the ROM stores a value of 1.

a) True
b) False
124.

PROM stands for

a) Programmable Read Only Memory.
b) Pre-fed Read Only Memory.
c) Pre-required Read Only Memory.
d) Programmed Read Only Memory.
125.

The PROM is more effective than ROM chips in regard to _______.

a) Cost
b) Memory management
c) Speed of operation
d) Both a and c
126.

The difference between the EPROM and ROM circuitory is _____.


a) The usage of MOSFET’s over transistors.
b) The usage of JFET’s over transistors.
c) The usage of an extra transistor.
d) None of the above.


127.

The ROM chips are mainly used to store _______.

a) System files
b) Root directories
c) Boot files
d) Driver files
128.

The maximum number of devices that can be connected to SCSI BUS is ______.

a) 16
b) 12
c) 8
d) 10
129.

The contents of the EPROM are earsed by

a) Overcharging the chip.
b) Exposing the chip to UV rays.
c) Exposing the chip to IR rays.

d) Discharging the Chip.
130.

The disadvantage of the EPROM chip is

a) The high cost factor.
b) The low efficiency.
c) The low speed of operation.
d) The need to remove the chip physically to reprogram it.
131.

EEPROM stands for Electrically Erasable Programmable Read Only Memory.

a) True
b) False
132.

The disadvantage of the EEPROM is/are

a) The requirement of different voltages to read,write and store information.
b) The Latency inread operation.
c) The inefficient memory mapping schemes used.
d) All of the above.


133.

The memory devices which are similar to EEPROM but differ in the cost

effectiveness is ______.

a) Memory sticks
b) Blue-ray devices
c) Flash memory
d) CMOS
134.

The ROM chips are mainly used to store _______.

a) System files
b) Boot files
c) Driver files
d) Root directories
135.

The only difference between the EEPROM and flash memory is that the latter

doesn’t allow bulk data to be written.
a) True
b) False
136.

The flash memories find application in ______.

a) Super computers
b) Mainframe systems
c) Distributed systems
d) Portable devices
137.

The memory module obtained by placing a number of flash chips for higher


memory storage called as _______.
a) FIMM
b) SIMM
c) Flash card
d) RIMM
138.

The DMA differs from the interrupt mode by?

a) The method accessing the I/O devices
b) The amount of data transfer possible