Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 736 2009-10-1
736 Index
System-in-FPGA (SIF) architecture, 352
System-level models
application model, 126
execution platform model, 127–129
illustration, 126
memory and power model, 129–130
performance analysis
analytic techniques, 6
design space exploration cycle, 4–5
distributed embedded platforms, 4
picture-in-picture (PiP)
application, 7–9
simulation-based methods, 5–6
task mapping, 129
System-on-chip (SoC)
ANNABELLE
average power consumption, 338
heterogeneous, 336–338
partial dynamic reconfiguration,
339
reference locality, 338–339
integrated multi-technology systems,
603–604
MONTIUM
average power consumption, 338
design methodology, 335–336
heterogeneous, 336–338
partial dynamic reconfiguration,
339

reconfigurable processing core,
333–335
reference locality, 338–339
MPSoC programming models
models, 238
primitives, 239
programming levels, 238
multiprocessor system, 331–333
platform progrmming models
advantages and drawbacks,
182–184
classes, 182
explicit capture of parallelism, 184
SiP design process, 606, 610–611
SystemC AMS extensions
architecture level, 591–592
cases, 591–592
code, 598–599
methodology-specific support,
595–596
open SystemC initiative (OSCI),
588–591
refinement activities, 592, 594
SystemC-based performance analysis
distributed embedded systems
analytical approaches, 29–30
hybrid approaches, 31–32
simulative approaches, 30–31
experimental results, 47–50
hybrid approach

advantages and disadvantages,
35–36
basic block, pipeline modelling,
40–43
dynamic correction, 43–45
software tasks, 46–47
static cycle calculation, 40
SystemC code annotation, 38–40
task switches, 46
WCET/BCET value, 36–38
outlook, 50
transaction-level modeling (TLM)
abstraction levels, 32
accuracy and speed trade-off,
33–34
SystemC-H design environment, 297
Systems in package (SiP), 604, 606,
610–611
T
Tagged signal model (TSM), 463
Task transaction level interface (TTL)
APIs, abstraction levels, 240
HW–SW component integration, 210
stream processing applications, 239
TDL, see Timing definition language
(TDL)
Tilera processor
design methodology, 347
features, 346
iMesh on-chip network, 346

tile64, 345
Time-triggered architecture (TTA), 94
Time-triggered networked control
system
control performance and network
schedule, 170
stand-alone network interface blocks,
169
Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 737 2009-10-1
Index 737
Timed automata
composition, 470–473
continuous/discrete co-simulation
tools, 535–536
model checking, exhaustive
verification
bounded-response property,
392–393
Büchi-automaton monitor, 395–396
difference bound matrices (DBMs),
395
discrete state-transition system,
393
properties type, 391–392
region graph abstraction, 393
state-explosion, 394
time-abstract quotient, 394–395
timed Büchi automata (TBA),
395–396
zone graph, 395

model-based design, 383–384
modeling
Alur–Dill model, 387–388
clock constraints, 388
discrete- vs. dense-time debate, 388
finite-state automaton, 386
operational semantics, 386–387
rendez-vous type, 388–389
timed and discrete transitions, 387
timed automaton (TA), 386
timing constraints, 386
untimed models, 389
operational semantics, 469–470
overview, 466–467
partial verification
exhaustive verification tools, 405
randomized exploration, 406–408
simulations, 405
state-explosion, 404–405
time-scalability properties,
405–406
semantic unit abstract data model,
467–469
TASU modeling language, 473–474
TDL modeling language, 475–481
test generation
analog-clock, 417–418
assumptions, 414
digital-clock, 417, 419–420
generic description, 416–417

input–output specification,
414–415
models, digital-clock, 418–419
system under test (SUT), 413–414,
420–421
test case, 416
tick model, 419–420
timed automata with inputs and
outputs (TAIO), 412–413
tioco framework, 415
testing, 411–412
timing definition language (TDL),
474–475
Timed automata with inputs and
outputs (TAIO), 412–413
Timed computation tree logic
(TCTL), 99
Timed data flow (TDF), 588–591
TimeProgressCS_TA method,
471–472
Timing definition language (TDL)
bind/createnew/delete, 476
execution trace, 479, 481
Giotto system, 474–475
GReAT transformation, 477–478,
479
logical execution time (LET), 474
MetaGME metamodels, 475
model, 479–480
pseudo-code, 479–480

timed automaton (TA), 476–477
transformation steps, 476
TinyGALS, 241
Transaction-level modeling (TLM)
abstraction levels, 32
accuracy and speed trade-off
communication refinement, 33–34
computation refinement, 34
TrueTime
advantages, 148
closed-loop control performance,
147
co-simulation tools, 149
constant bandwidth server (CBS)
experiments, 157–159
implementation, 156–157
updating rules, 156
feedback control, 146
Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 738 2009-10-1
738 Index
kernel block features
discrete PI-controller, 154
initialization script and code
functions, 153
scheduling algorithms, 153
library, 147
limitations and extensions
execution times, 171–172
higher-layer protocols, 173
simulation platform, 173

single-core assumption, 170–171
single-thread execution, 172–173
mobile robots in sensor networks
bus communication, 164
complete model, 165–167
evaluation, 167–168
hardware models, 161–163
physical scenario, 161
radio communication, 164–165
simulation model, 160–161
software components, 160
network block features
types and uses, 155
wireless networks, 155–156
network simulators, 148–149
ns-2 discrete-event simulator, 148
pure scheduling simulator, 148
sampled control theory, 146
SimEvents
R

2 toolbox, 149
Simics system, 149
simulation, 146
time-triggered networked control
system
control performance and network
schedule, 170
stand-alone network interface
blocks, 169

timing and execution models
implementation, 150
kernel simulators, 151–152
network simulators, 152
TTA, see Time-triggered architecture
TTL, see Task transaction level interface
U
UML/XML implementation
AMS/MT IP blocks, 618–620, 622
class diagram, 620–621
object management group (OMG),
618–619
Rune
II
, 618–619
UMTS, see Universal mobile
telecommunications system
Universal mobile telecommunications
system (UMTS)
architectural modeling
architecture models, 304–306
operating system (OS) scheduling
policies, 304
functional modeling
illustration, 302
mechanisms, 302–303
medium access control (MAC), 301
radio link control (RLC), 301
mapped system, 306
results

estimated execution time
vs. utilization, 306–309
event analysis, 311–312
first-come-first-serve (FCFS)
scheduling, 309
METRO II simulation phases,
310–311
models, 306
priority-based scheduling, 308
round-robin scheduling, 306
runtime analysis, 310–311
UpdateTimeGuardTA method, 470
UPPAAL
advantages, 539–540
attributes, 100
framework model
abstract task and resource models,
102–103
data structures, 103–104
resource template, 107–109
task template and graphs,
104–107
instantiation
schedulability problem,
114–115
schedulability query, 113
modeling language
features and stopwatches, 99
timed computation tree logic
(TCTL), 99

train-gate model, 96–98
Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 739 2009-10-1
Index 739
MoVES analysis framework
operating models, 123
support, 135–136
real-time model checking, 94
resources, 101–102
single-processor systems, 94
task dependencies, 100–101
time-triggered architecture (TTA), 94
Upper event-arrival function, η
+
,61
V
Variability characterization curves
(VCCs)
arrival and service curves, 13–14
compact representation, 19–22
Verilog hardware description language
(VHDL), 623
VHDL-AMS
accelerometer
description, 704–706
IBIS drivers, 708, 710–711, 714
interface, 711
output circuitry, 706–708, 709, 710,
711, 712, 713, 714
application, 702–704
distributed architecture, 698–700

gyroscope, 711, 713
microelectromechanical systems
(MEMS), 697–698
design methodology, 700–702
models, 698
simulation
and validation, 716, 717
gyroscope, 715–717
IBIS drivers, 714–715
Virtex 4 FX 100 device, 372–373, 374
X
Xilinx MPMC, 367
Z
Zero-crossing callback function, 150
Nicolescu/Model-Based Design for Embedded Systems 67842_C022 Finals Page 740 2009-10-1