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686 Model-Based Design for Embedded Systems
rst
Clock&Reset
1
0
MM M
X
X01234
01
01
03
03
03
03
03
03
56789ABCDEF
977
250 μm
XX
XX
XX
XX
Now
8000000 pa
XXX
0
0
0
0

00
00
00
00
0
0
0
00
00
00
00
1
clk
Configuration control
D
valid
iond
en
clk_gel
pattern
sel
Input from Fiber/circuits
Output from Fiber/circuits
input_0
input_1
input_2
input_3
output_0
output_1
output_2

output_3
Clock & Reset
FIGURE 20.28
FIG test system block diagram: Areas in the digital domain are executed in
ModelSim while areas in the analog and optical domains are executed in
Chatoyant.
CLk4X
CLk4X
Data1
PIN PD
array
Receiver
circuitry
8:1 DDR
deserializer
1:8 DDR
Serializer
1:8 DDR
Serializer
8:1 DDR
deserializer
Dout
(7:0)
Dout
(15:8)
Clk1X_Out
RXTX
Driver
circuitry
4 free-space

optical links
Electrical output
Electrical input
Din
(7:0)
Din
(15:8)
Clk1X_IN
Clk4X_IN
VCSEL
array
Data2
FIGURE 20.29
SPOT system block diagram showing the digital data entering in parallel
to the UTSI transceiver chip, serialized transmitted over free-space optics,
deserialized with clock-recovery, back into parallel data. (Courtesy of [52].)
propagated light back into analog signals at which point the analog circuits
amplify and feed the de-serializing logic in the digital domain. Figure 20.29
shows the system block diagram.
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SPOT tests the ability of the co-simulation environment to work with
a global clock signal. This clock signal, generated by the digital domain,
is transmitted with the data, and thus crosses the co-simulation interface.
This means that there are a large number of periodic events occurring. This
illustrates the simulation behavior of a synchronous system versus an asyn-
chronous system in the co-simulation environment.
Given these two systems, we next show the results of runtimes and event
traffic for different time resolutions of the SYNC_PULSE parameter. A total
of four resolutions were tested, 1 ps, 10 ps, 100 ps, and 1 ns. These values

were chosen since the systems run at relatively high frequencies, in the range
of nanoseconds for both data bit rate and clock speed. All simulations were
performed on a Dual 1.70 MHz Intel Xeon Processor Dell Precision with 3
GBs of RAM running Red Hat Linux 7.3, kernel version 2.4.18-3SMP.
20.3.2.3 FIG Runtimes
The following set of charts show the runtime and event traffic seen in each
of the resolution steps. Figure 20.30 shows the runtime, in seconds versus
the four different time resolutions. Figure 20.31 shows the event counts seen
from the Chatoyant and ModelSim perspectives.
As seen in Figure 20.30, the runtimes decreased as the resolution became
coarser. One thing to note is the logarithmic-like decay. This is most likely
because of the total simulation time of the experiment rather than the time
resolution. Since all simulations were performed for a simulation time of
154.22 141.01163.75214.43
100 ps 1 ns10 ps1 ps
0.00
50.00
100.00
150.00
200.00
250.00
Series1
Seconds
Runtime vs. sync resolution
FIGURE 20.30
Runtime versus Sync resolution for FIG.
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688 Model-Based Design for Embedded Systems
Chatoyant RX
0

1000
2000
3000
4000
5000
Number of events vs. resolution
Event count
Chatoyant TX
ModelSim RX
ModelSim TX
4
1 ps Sync
1,077
4,307
12
4
10 ps Sync
37
147
12
4
100 ps Sync
8
32
12
4
1 ns Sync
4
16
12

FIGURE 20.31
Number of events per simulation for FIG.
1.4 us, the closer the granularity of the resolution is to the magnitude of the
end time, the smaller the difference will be in runtimes. This is explained
by the notion that less event processing is performed since more events are
ignored between synchronization points. Therefore, event processing over-
head is reduced.
Also, the amount of event traffic decreases by two orders of magnitude
between 1 ps and 1 ns resolutions. This is also related to the fact that more
events are processed at higher resolutions.
20.3.2.4 SPOT Runtimes
The SPOT system yields a different perspective on the co-simulation system.
Figure 20.32 shows the runtime results versus resolution and Figure 20.33
shows the event traffic at each resolution.
As seen in Figure 20.32, the runtimes do decrease, in general, with respect
to an increasing granularity. The exception to this is the 10 ps resolution,
which shows a slight increase in runtime compared to the 1 ps resolution.
This may be because of the processing of more event changes given the peri-
odicity of the clock signal in the system. Regardless of this outlier, there is
still a general trend for decreasing runtimes as well as decreased event traf-
fic with lower resolutions.
SPOT having a higher runtime versus FIG indicates the effect of the
clock signal on performance. Since there is a clock having a consistent event
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Seconds
0.00
200.00
400.00
600.00

800.00
1000.00
1200.00
1400.00
1600.00
1800.00
2000.00
Runtime vs. sync resolution
1 ps 10 ps 100 ps 1 ns
1605.67 1722.50 843.31 842.65
FIGURE 20.32
Runtime results versus resolution granularity.
change at a fixed frequency, the number of events per synchronization cycle
increases. This is seen by the higher event counts in each SPOT simulation
versus those for FIG. This amount, spread uniformly across the entire simu-
lation in SPOT, versus FIG which has dense cluster of events separated by a
large time gap, exemplifies the overhead associated with processing events.
20.4 Summary
In summary, we have presented a co-simulation environment for mixed-
domain, mixed-signal simulation that spans the realms of HDL digital logic,
analog electrical, optical, and mechanical systems. A variety of modeling
techniques are used to develop analog component models that are evalu-
ated using continuous time models. These component behaviors commu-
nicate via specific ports that pass complex messages between components.
Those messages, and the corresponding execution of the component mod-
els, are coordinated by a DE simulation backbone. This backbone, built
on Ptolemy, also runs in coordination with a commercial HDL simulator.
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690 Model-Based Design for Embedded Systems
4000

3500
3000
2500
2000
1500
1000
500
0
1 ps Sync
146
Chatoyant RX
Chatoyant TX
ModelSim RX
ModelSim TX
146 146 142
175
175
144
3499 3499 1750
179435433543
150 150 150
10 ps Sync 100 ps Sync 1 ns Sync
Number of events vs. resolution
Event count
FIGURE 20.33
Event traffic versus resolution granularity.
This system, known as Chatoyant–ModelSim Co-Simulation Environment,
provides an interface between the multi-domain analog realm handled by
Chatoyant and the digital realm, handled by ModelSim.
As seen in the co-simulation experiments, there are a few factors that

affect runtime performance. Asynchronous systems with more clustering of
events within certain windows generally have a better runtime than syn-
chronous systems that have a steady load of events. Also, as predicted, the
resolution of synchronization, defined in the context of the PDES conserva-
tive approach and implemented using Unix IPC, has an effect on runtime
performance by reducing the event processing overhead, at the cost of accu-
racy. This cost is assessed based on the system and requirements a particular
user has for the simulation.
20.4.1 Conclusions
Multi-domain modeling and multi-rate simulation tools are required to sup-
port mixed-technology system design. This chapter has shown Chatoyant’s
support for simulating and analyzing optical MEM systems with models
for optical, electrical, and mechanical models for components and signals.
By supporting a variety of component and signal modeling techniques and
multiple abstraction levels, Chatoyant has the ability to perform and ana-
lyze mixed-signal tradeoffs, which makes it valuable to multi-technology
system designers. Keeping simulations, along with analysis techniques such
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as Monte Carlo for mechanical tolerancing, BER, crosstalk, and insertion loss
within the Chatoyant framework allows for quick and efficient system-level
design and analysis for the future development of next generation MDSoCs.
Acknowledgments
The work in this chapter was supported by DARPA, under Grant No. F3602-
97-2-0122 and NSF, under Grant No. ECS-9616879 and CCR 88319. The Uni-
versity of Delaware is acknowledged for providing the SPOT system data for
testing.
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