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316 Model-Based Design for Embedded Systems
embedded systems. We argued in favor of the need of a unified way of
thinking about system design as the basis for a novel system science. One
approach was presented, the PBD, that aims at achieving that unifying role.
We discussed some of the most promising approaches for chip and embed-
ded system design in the PBD perspective. M
ETROPOLIS and its successor
M
ETRO II frameworks were presented. Some examples of METRO II applica-
tions to different industrial domains were then described.
While we believe we are making significant inroads, much work remains
to be done to transfer the ideas and approaches that are flourishing today in
research and in advanced companies to the generality of IC and embedded
system designers. To be able to do so,
• We need to further advance the understanding of the relationships
among parts of a heterogeneous design and its interaction with the
physical environment.
• The efficiency of algorithms and tools must be improved to offer a solid
foundation to the users.
• Models and use cases have to be developed.
• The scope of system-level design must be extended to include fault
tolerance, security, and resiliency.
• The EDA industry has to embrace the new paradigms and venture into
unchartered waters to grow beyond where it is today. It must create the
necessary tools to help engineers to apply the new paradigms.
• Academia must develop new curricula (e.g., [13]) that favor a broader
approach to engineering while emphasizing the importance of founda-
tional disciplines such as mathematics and physics; embedded system
designers require a broad view and the capability of mastering hetero-
geneous technologies.

• The system and semiconductor industry must recognize the impor-
tance of investing in training and tools for their engineers to be able
to bring new products and services to market.
Acknowledgments
We wish to acknowledge the support of the Gigascale System Research Cen-
ter, the support of NSF-sponsored Center for Hybrid and Embedded Soft-
ware Systems, the support of the EU networks of excellence ARTIST and
HYCON, and of the European community project SPEEDS. The past and the
present support of General Motors, Infineon, Intel, Pirelli, ST, Telecom Italia
(in particular, Marco Sgroi, Fabio Bellifemine, and Fulvio Faraci), UMC, and
United Technologies Corporation (in particular, the strong interaction with
Clas Jacobson, John F. Cassidy Jr., and Michael McQuade) is also gratefully
acknowledged.
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Platform-Based Design and Frameworks: METROPOLIS and METRO II 317
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11
Reconfigurable Multicore Architectures for
Streaming Applications
Gerard J. M. Smit, André B. J. Kokkeler, Gerard K. Rauwerda,
and Jan W. M. Jacobs
CONTENTS
11.1 Introduction 324
11.1.1 Streaming Applications 324
11.1.2 Multicore Architectures 325
11.1.2.1 Heterogeneous Multicore SoC 327
11.1.3 Design Criteria for Streaming Applications 327
11.1.3.1 Predictable and Composable 327
11.1.3.2 Energy Efficiency 328
11.1.3.3 Programmability 329
11.1.3.4 Dependability 330
11.2 Classification 330
11.3 Sample Architectures 333
11.3.1 M
ONTIUM/ANNABELLE System-on-Chip 333
11.3.1.1 M
ONTIUM ReconfigurableProcessingCore 333
11.3.1.2 Design Methodology 335
11.3.1.3 A
NNABELLE HeterogeneousSystem-on-Chip 336
11.3.1.4 Average Power Consumption 338
11.3.1.5 Locality of Reference 338
11.3.1.6 Partial Dynamic Reconfiguration 339
11.3.2 Aspex Linedancer 339

11.3.2.1 ASProCore Architecture 341
11.3.2.2 Linedancer Hardware Architecture 341
11.3.2.3 Design Methodology 342
11.3.3 PACT-XPP . 343
11.3.3.1 Architecture 343
11.3.3.2 Design Methodology 344
11.3.4 Tilera 345
11.3.4.1 Design Methodology 346
11.4 Conclusion 347
References 347
323
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324 Model-Based Design for Embedded Systems
11.1 Introduction
This chapter addresses reconfigurable heterogenous and homogeneous
multicore system-on-chip (SoC) platforms for streaming digital signal pro-
cessing applications, also called streaming DSP applications. In streaming
DSP applications, computations can be specified as a data flow graph with
streams of data items (the edges) flowing between computation kernels (the
nodes). Most signal processing applications can be naturally expressed in
this modeling style [14]. Typical examples of streaming DSP applications
are wireless baseband processing, multimedia processing, medical image
processing, sensor processing (e.g., for remote surveillance cameras), and
phased array radars. In a heterogeneous multicore architecture, a core can
either be a bit-level reconfigurable unit (e.g., FPGA), a word-level reconfig-
urable unit, or a general-purpose programmable unit (digital signal proces-
sor (DSP) or general purpose processor (GPP)). We assume the cores of the
SoC are interconnected by a reconfigurable network-on-chip (NoC). The pro-
grammability of the individual cores enables the system to be targeted at
multiple application domains.

We take a holistic approach, which means that all aspects of system
design need to be addressed simultaneously in a systematic way (e.g., [24]).
We believe that this is key for an efficient overall solution, because an inter-
esting optimization in a small corner of the design might lead to inefficiencies
in the overall design. For example, the design of the NoC should be coordi-
nated with the design of the processing cores, and the design of the process-
ing cores should be coordinated with the tile specific compilers. Eventually,
there should be a tight fit between the application requirements and the SoC
and NoC capabilities.
We first introduce streaming applications and multicore architectures in
Sections 11.1.1 and 11.1.2, next we present key design criteria for streaming
applications in Section 11.1.3. After that we give a multidimensional classi-
fication of architectures for streaming applications in Section 11.2. For each
category, one or more sample architectures are presented in Section 11.3. We
end this chapter with a conclusion.
11.1.1 Streaming Applications
The focus of this chapter is on multicore SoC architectures for streaming
DSP applications where we can assume that the data streams are semi-static
and have a periodic behaviour. This means that for a long period of time
subsequent data items of a stream follow the same route through the SoC.
The common characteristics of typical streaming DSP applications are as
follows:
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Reconfigurable MultiCore Architectures 325
• They are characterized by a relatively simple local processing of a huge
amount of data. The trend is that energy costs for data communication
dominates energy costs of processing.
• Data arrives at nodes at a rather fixed rate, which causes periodic data
transfers between successive processing blocks. The resulting com-
munication bandwidth is application dependent and a large variety

of communication bandwidth is required. The size of the data items
is application dependent (e.g., 14-bit samples for a sensor system, 64
32-bit words for HiperLAN/2 [15] OFDM symbols, or 8 × 8 × 24-bit
macro blocks for a video application). Also the data rate is application
dependent (e.g., 100 Msamples/sec after the A/D converter for a sen-
sor system, 200k OFDM symbols per second for HiperLAN/2, and 50
frames/sec for video).
• The data flows through the successive processes in a pipelined fash-
ion. Processes may work in parallel on parallel processors or can be
time-multiplexed on one or more processors. Therefore, streaming
applications show a predictable temporal and spatial behavior.
• For our application domains, typically throughput guarantees (in data
items per sec) are required for communication as well as for processing.
Sometimes latency requirements are also given.
• The lifetime of a communication stream is semi-static, which means a
stream is fixed for a relatively long time.
11.1.2 Multicore Architectures
Flexible and efficient SoCs can be realized by integrating hardware blocks
(called tiles or cores) of different granularities into heterogeneous recon-
figurable SoCs. In this chapter the term “core” is used for processor-like
hardware blocks and the term “tile” is used for ASICs, fine-grained recon-
figurable blocks, and memory blocks. We assume that the interconnected
building blocks can be heterogeneous (see Figure 11.1), for instance, bit-
level reconfigurable tiles (e.g., embedded FPGAs), word-level reconfig-
urable cores (e.g., domain-specific reconfigurable cores), general-purpose
programmable cores (e.g., DSPs and GPPs), and memory blocks. From a
systems point of view these architectures are heterogeneous multiproces-
sor systems on a single chip. The programmability and reconfigurability of
the architecture enables the system to be targeted at multiple application
domains. Recently, a number of multicore architectures have been proposed

for the streaming DSP application domain. Some examples will be discussed
in Section 11.3.
A multicore approach has a number of advantages:
• It is a future-proof architecture as the processing cores do not grow in
complexity with technology. Instead, as technology scales, simply the
number of cores on the chip grows.