The
Computer Engineering
Handbook
Second Edition
Edited by
Vojin G. Oklobdzija
Digital Design and Fabrication
Digital Systems and Applications
Vojin Oklobdzija/Digital Design and Fabrication 0200_C000 Final Proof page i 19.10.2007 11:16pm Compositor Name: TSuresh
Computer Engineering Series
Series Editor: Vojin G. Oklobdzija
Coding and Signal Processing for
Magnetic Recording Systems
Edited by Bane Vasic and Erozan M. Kurtas
The Computer Engineering Handbook
Second Edition
Edited by Vojin G. Oklobdzija
Digital Image Sequence Processing,
Compression, and Analysis
Edited by Todd R. Reed
Low-Power Electronics Design
Edited by Christian Piguet
Vojin Oklobdzija/Digital Design and Fabrication 0200_C000 Final Proof page ii 19.10.2007 11:16pm Compositor Name: TSuresh
DIGITAL DESIGN
AND FABRICATION
Edited by
Vojin G. Oklobdzija
University of Texas
Vojin Oklobdzija/Digital Design and Fabrication 0200_C000 Final Proof page iii 19.10.2007 11:16pm Compositor Name: TSuresh
CRC Press

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Library of Congress Cataloging-in-Publication Data
Digital design and fabrication / Vojin Oklobdzija.
p. cm.
Includes bibliographical references and index.
ISBN 978-0-8493-8602-2 (alk. paper)
1. Computer engineering. 2. Production engineering. I. Oklobdzija, Vojin G. II. Title.
TK7885.D54 2008
621.39 dc22 2007023256

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Preface
Purpose and Background
Computer engineering is a vast field spanning many aspects of hardware and software; thus, it is difficult
to cover it in a single book. It is also rapidly changing requiring constant updating as some aspects of it
may become obsolete. In this book, we attempt to capture the long lasting fundamentals as well as the
new trends, directions, and developments. This book could easily fill thousands of pages. We are aware
that some areas were not given sufficient attention and some others were not covered at all. We plan to
cover these missing parts as well as more specialized topics in more details with new books under the
computer engineering series and new editions of the current book. We believe that the areas covered by
this new edition are covered very well because they are written by specialists, recognized as leading
experts in their fields.
Organization
This book contains five sections. First, we start with the fabrication and technology that have been a
driving factor for the electronic industry. No sector of the industry has experienced such tremendous
growth and advances as the semiconductor industry did in the past 30 years. This progress has surpassed
what we thought to be possible, and limits that were once thought of as fundamental were broken several
times. This is best seen in the development of semiconductor memories, described in Section II.
When the first 256-kbit DRAM chips were introduced, the ‘‘alpha particle scare’’ (the problem encoun-
tered with alpha particles discharging the memory cell) predicted that radiation effects would limit
further scaling in dimensions of memory chips. Twenty years later, the industry was producing 256-Mbit
DRAM chips—a thousand times improvement in density—and we see no limit to further scaling even at
4GB memory capacit y. In fact, the memory capacity has been tripling every 2 years while the number of
transistors in the processor chip has been doubling every 2 years.
Important design techniques are described in two separate sections. Section III addresses design
techniques used to create modern computer systems. The most important design issues starting from

timing and clocking, PLL and DLL design and ending with high-speed computer arithmetic and high-
frequency design are described in this section. Section IV deals with power consumed by the system.
Power consumption is becoming the most important issue as computers are start ing to penetrate large
consumer product markets, and in several cases low-power consumption is more important than the
performance that the system can deliver.
Finally, reliability and testability of computer systems are described in Section V.
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v
Locating Your Topic
Several avenues are available to access desired information. A complete table of contents is presented at
the front of the book. Each of the sections is preceded with an individual table of contents. Finally, each
chapter begins with its own table of contents. Each contributed chapter contains comprehensive
references. Some of them contain a ‘‘To Probe Further’’ section, in which a general discussion of various
sources such as books, journals, magazines, and periodicals is located. To be in tune with the modern
times, some of the authors have also included Web pointers to valuable resources and information. We
hope our readers will find this to be appropriate and of much use.
A subject index has been compiled to provide a means of accessing information. It can also be used
to locate definitions. The page on which the definition appears for each key defining term is given in
the index.
This book is designed to provide answers to most inquiries and to direct inquirers to further sources
and references. We trust that it will meet the needs of our readership.
Acknowledgments
The value of this book is based entirely on the work of people who are regarded as top experts in their
respective field and their excellent contributions. I am grateful to them. They contributed their valuable
time without compensation and with the sole motivation to provide learning material and help
enhance the profession. I would like to thank Saburo Muroga, who provided editorial adv ice, reviewed
the content of the book, made numerous suggestions, and encouraged me. I am indebted to him as well
as to other members of the advisory board. I would like to thank my colleague and friend Richard Dorf
for asking me to edit this book and trusting me with this project. Kristen Maus worked tirelessly on the
first edition of this book and so did Nora Konopka of CRC Press. I am also grateful to the editorial staff

of Taylor & Francis, Theresa Delforn and Allison Shatkin in particular, for all the help and hours spent
on improving many aspects of this book. I am particularly indebted to Suryakala Arulprakasam and her
staff for a superb job of editing, which has substantially improved this book over the previous one.
Vojin G. Oklobdzija
Berkeley, California
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vi
Editor
Vojin G. Oklobdzija is a fellow of the Institute of Electrical and
Electronics Engineers and distinguished lecturer of the IEEE Solid-
State Circuits and IEEE Circuits and Systems Societies. He received his
PhD and MSc from the University of California, Los Angeles in 1978
and 1982, as well as a Diplom-Ingenieur (MScEE) from the Electrical
Engineering Department, University of Belgrade, Yugoslavia in 1971.
From 1982 to 1991, he was at the IBM T.J. Watson Research Center
in New York where he made contributions to the development of
RISC architecture and processors. In the course of this work he
obtained a patent on register-renaming, which enabled an entire
new generation of superscalar processors.
From 1988 to 1990, he was a visiting faculty at the University of California, Berkeley, while on leave
from IBM. Since 1991, Professor Oklobdzija has held various consulting positions. He was a consultant
to Sun Microsystems Laboratories, AT&T Bell Laboratories, Hitachi Research Laboratories, Fujitsu
Laboratories, Samsung, Sony, Silicon Systems=Texas Instruments Inc., and Siemens Corp., where he
was also the principal architect of the Siemens=Infineon’s TriCore processor.
In 1996, he incorporated Integration Corp., which delivered several successful processor and encryp-
tion processor designs.
Professor Oklobdzija has held various academic appointments, in addition to the one at the University
of California. In 1991, as a Fulbright professor, he helped to develop programs at universities in South
America. From 1996 to 1998, he taught courses in Silicon Valley through the University of California,
Berkeley Extension, and at Hewlett–Packard. He was visiting professor in Korea, EPFL in Switzerland and

Sydney, Australia. Currently he is Emeritus professor at the University of California and Research
professor at the University of Texas at Dallas.
He holds 14 U.S. and 18 international patents in the area of computer architecture and design.
Professor Oklobdzija is a member of the American Association for the Advancement of Science, and
the American Association of University Professors.
He serves as associate editor for the IEEE Transactions on Circuits and Systems II; IEEE Micro; and
Journal of VLSI Signal Processing; International Symposium on Low-Power Electronics, ISLPED; Computer
Arithmetic Symposium, ARITH, and numerous other conference committees. He served as associate
editor of the IEEE Transactions on Computers (2001–2005), IEEE Transactions on Very Large Scale of
Integration (VLSI) Systems (1995–2003), the ISSCC Digital Program Committee (1996–2003), and the
first Asian Solid-State Circuits Conference, A-SSCC in 2005. He was a general chair of the 13th
Symposium on Computer Arithmetic in 1997.
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vii
He has published over 150 papers in the areas of circuits and technology, computer arithmetic, and
computer architecture, and has given over 150 invited talks and short courses in the United States,
Europe, Latin America, Australia, China, and Japan.
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viii
Editorial Board
Krste Asanovic
´
University of California at Berkeley
Berkeley, California
William Bowhill
Intel Corporation
Shrewsbury, Massachusetts
Anantha Chandrakasan
Massachusetts Institute of Technology
Cambridge, Massachusetts

Hiroshi Iwai
Tokyo Institute of Technology
Yokohama, Japan
Saburo Muroga
University of Illinois
Urbana, Illinois
Kevin J. Nowka
IBM Austin Research Laboratory
Austin, Texas
Takayasu Sakurai
University of Tokyo
Tokyo, Japan
Alan Smith
University of California at Berkeley
Berkeley, California
Ian Young
Intel Corporation
Hillsboro, Oregon
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Contributors
Cyrus (Morteza) Afghahi
Broadcom Corporation
Irvine, California
Chouki Aktouf
Institute Universitaire de Technologie
Valex, France
William Athas
Apple Computer Inc.

Sunnyvale, California
Shekhar Borkar
Intel Corporation
Hillsboro, Oregon
Thomas D. Burd
AMD Corp.
Sunnyvale, California
R. Chandramouli
Synopsys Inc.
Mountain View, California
K. Wayne Current
University of California
Davis, California
Foad Dabiri
University of California at Los Angeles
Los Angeles, California
Vivek De
Intel Corporation
Hillsboro, Oregon
Gensuke Goto
Yamagata University
Yamagata, Japan
James O. Hamblen
Georgia Institute of Technology
Atlanta, Georgia
Hiroshi Iwai
Tokyo Institute of Technology
Yokohama, Japan
Roozbeh Jafar i
University of Texas at Dallas

Dallas, Texas
Farzin Michael Jahed
Toshiba America Electronic Components
Irvine, California
Shahram Jamshidi
Intel Corporation
Santa Clara, California
Eugene John
University of Texas at San Antonio
San Antonio, Texas
Yuichi Kado
NIT Telecommunications Technology
Laboratories
Kanagawa, Japan
James Kao
Intel Corporation
Hillsboro, Oregon
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xi
Ali Keshavarzi
Intel Corporation
Hillsboro, Oregon
Fabian Klass
PA Microsystems
Palo Alto, California
Tadahiro Kuroda
Keio University
Keio, Japan
Hai Li
Intel Corporation

Santa Clara, California
John George Maneatis
True Circuits, Inc.
Los Altos, California
Dejan Markovic
´
University of California at Los Angeles
Los Angeles, California
Tammara Massey
University of California at Los Angeles
Los Angeles, California
John C. McCallum
National University of Singapore
Singapore, Singapore
Masayuki Miyazaki
Hitachi, Ltd.
Tokyo, Japan
Ani Nahapetian
University of California at Los Angeles
Los Angeles, California
Raj Nair
Intel Corporation
Hillsboro, Oregon
Siva Narendra
Intel Corporation
Hillsboro, Oregon
Kevin J. Nowka
IBM Austin Research Laboratory
Austin, Texas
Shun-ichiro Ohmi

Tokyo Institute of Technology
Yokohama, Japan
Rakesh Patel
Intel Corporation
Santa Clara, California
Christian Piguet
Centre Suisse d’Electronique et de Microtechnique
Neuchatel, Switzerland
Kaushik Roy
Purdue University
West Lafayette, Indiana
Majid Sarrafzadeh
University of California at Los Angeles
Los Angeles, California
Katsunori Seno
Sony Corporation
Tokyo, Japan
Kinyip Sit
Intel Corporation
Santa Clara, California
Hendrawan Soeleman
Purdue University
West Lafayette, Indiana
Dinesh Somasekhar
Intel Corporation
Hillsboro, Oregon
Zoran Stamenkovic
´
IHP GmbH—Innovations for High Performance
Microelectronics

Frankfurt (Oder), Germany
N. Stojadinovic
´
University of Nis
ˇ
Nis
ˇ
, Serbia
Earl E. Swartzlander, Jr.
University of Texas at Austin
Austin, Texas
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xii
Zhenyu Tang
Intel Corporation
Santa Clara, California
Nestoras Tzartzanis
Fujitsu Laboratories of America
Sunnyvale, California
H.T. Vierhaus
Brandenburg University of Technology at Cottbus
Cottbus, Germany
Shunzo Yamashita
Hitachi, Ltd.
Tokyo, Japan
Yibin Ye
Intel Corporation
Hillsboro, Oregon
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xiii

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Contents
SECTION I Fabrication and Technology
1 Trends and Projections for the Future of Scaling and Future Integration
Trends Hiroshi Iwai and Shun-ichiro Ohmi
1-1
2 CMOS Circuits
2.1 VLSI Circuits Eugene John 2-1
2.2 Pass-Transistor CMOS Circuits Shunzo Yamashita 2-21
2.3 Synthesis of CMOS Pass-Transistor Logic Dejan Markovic
´
2-39
2.4 Silicon on Insulator Yuichi Kado 2-52
3 High-Speed, Low-Power Emitter Coupled Logic Circuits Tadahiro Kuroda 3-1
4 Price-Performance of Computer Technology John C. McCallum 4-1
SECTION II Memory and Storage
5 Semiconductor Memory Circuits Eugene John 5-1
6 Semiconductor Storage Devices in Computing and Consumer
Applications Farzin Michael Jahed
6-1
SECTION III Design Techniques
7 Timing and Clocking
7.1 Design of High-Speed CMOS PLLs and DLLs John George Maneatis 7-1
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xv
7.2 Latches and Flip-Flops Fabian Klass 7-33
7.3 High-Performance Embedded SRAM Cyrus (Morteza) Afghahi 7-71
8 Multiple-Valued Logic Circuits K. Wayne Current 8-1
9 FPGAs for Rapid Prototyping James O. Hamblen 9-1
10 Issues in High-Frequency Processor Design Kevin J. Nowka 10-1

11 Computer Arithmetic
11.1 High-Speed Computer Arithmetic Earl E. Swartzlander, Jr. 11-1
11.2 Fast Adders and Multipliers Gensuke Goto 11-21
SECTION IV Design for Low Power
12 Design for Low Power Hai Li, Rakesh Patel, Kinyip Sit, Zhenyu Tang,
and Shahram Jamshidi
12-1
13 Low-Power Circuit Technologies Masayuki Miyazaki 13-1
14 Techniques for Leakage Power Reduction Vivek De, Ali Keshavarzi,
Siva Narendra, Dinesh Somasekhar, Shekhar Borkar, James Kao, Raj Nair,
and Yibin Ye
14-1
15 Dynamic Voltage Scaling Thomas D. Burd 15-1
16 Lightweight Embedded Systems Foad Dabiri, Tammara Massey,
Ani Nahapetian, Majid Sarrafzadeh, and Roozbeh Jafari
16-1
17 Low-Power Design of Systems on Chip Christian Piguet 17-1
18 Implementation-Level Impact on Low-Power Design Katsunori Seno 18-1
19 Accurate Power Estimation of Combinational CMOS Digital Circuits
Hendrawan Soeleman and Kaushik Roy
19-1
20 Clock-Powered CMOS for Energy-Efficient Computing
Nestoras Tzartzanis and William Athas
20-1
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xvi
SECTION V Testing and Design for Testability
21 System-on-Chip (SoC) Testing: Current Practices and Challenges
for Tomorrow R. Chandramouli
21-1

22 Test Technology for Sequential Circuits H.T. Vierhaus
and Zoran Stamenkovic
´

22-1
23 Scan Testing Chouki Aktouf 23-1
24 Computer-Aided Analysis and Forecast of Integrated Circuit Yield
Zoran Stamenkovic
´
and N. Stojadinovic
´

24-1
Index I-1
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xvii
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I
Fabrication
and Technology
1 Trends and Projections for the Future of Scaling and Future
Integration Trends Hiroshi Iwai and Shun-ichiro Ohmi 1-1
Introduction
.
Downsizing below 0.1 mm
.
Gate Insulator
.
Gate Electrode
.

Source and Drain
.
Channel Doping
.
Interconnects
.
Memory Technology
.
Future Prospects
2 CMOS Circuits Eugene John, Shunzo Yamashita, Dejan Markovic
´
,
and Yuichi Kado 2-1
VLSI Circuits
.
Pass-Transistor CMOS Circuits
.
Synthesis of CMOS
Pass-Transistor Logic
.
Silicon on Insulator
3 High-Speed, Low-Power Emitter Coupled Logic Circuits Tadahiro Kuroda 3-1
Active Pull-Down ECL Circuits
.
Low-Voltage ECL Circuits
4 Price-Performance of Computer Technology John C. McCallum 4-1
Introduction
.
Computer and Integrated Circuit Technology
.

Processors
.
Memory and Storage—The Memory Hierarchy
.
Computer Systems—Small
to Large
.
Summary
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I-1
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1
Trends and Projections
for the Future
of Scaling and Future
Integration Trends
Hiroshi Iwai
Shun-ichiro Ohmi
Tokyo Institute of Technology
1.1 Introduction 1-1
1.2 Downsizing below 0.1 mm 1-3
1.3 Gate Insulator 1-11
1.4 Gate Electrode 1-16
1.5 Source and Drain 1-17
1.6 Channel Doping 1-19
1.7 Interconnects 1-20
1.8 Memory Technology 1-23
1.9 Future Prospects 1-25
1.1 Introduction
Recently, information technolog y (IT)—such as Internet, i-mode, cellular phone, and car navigation—

has spread very rapidly all over of the world. IT is expected to dramatically raise the efficiency of our
society and greatly improve the quality of our life. It should be noted that the progress of IT entirely owes
to that of semiconductor technology, especially Silicon LSIs (Large Scale Integrated Circuits). Silicon
LSIs provide us high speed=frequency operation of tremendously many functions with low cost, low
power, small size, small weight, and high reliability. In these 30 years, the gate length of the metal oxide
semiconductor field effect transistors (MOSFETs) has reduced 100 times, the density of DRAM
increased 500,000 times, and clock frequency of MPU increased 2,500 times, as shown in Table 1.1.
Without such a marvelous progress of LSI technologies, today’s great success in information technology
would not be realized at all.
The origin of the concept for solid-state circuit can be traced back to the beginning of last century, as
shown in Fig. 1.1. It was more than 70 years ago, when J. Lilienfeld using Al=Al
2
O
3
=Cu
2
S as an MOS
structure invented a concept of MOSFETs. Then, 54 years ago, first transistor (bipolar) was realized
using germanium. In 1960, 2 years after the invention of integrated circuits (IC), the first MOSFET was
realized by using the Si substrate and SiO
2
gate insulator [1]. Since then Si and SiO
2
became the key
materials for electronic circuits. It takes, however, more than several years until the Silicon MOSFET
evolved to Silicon ICs and further grew up to Silicon LSIs. The Silicon LSIs became popular in the
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1-1
market from the beginning of 1970s as a 1 kbit DRAM and a 4 bit MPU (microprocessor). In the early
1970s, LSIs started by using PMOS technology in which threshold voltage control was easier, but soon

the PMOS was replaced by NMOS, which was suitable for high speed operation. It was the middle of
1980s when CMOS became the main stream of Silicon LSI technology because of its capability for low
power consumption. Now CMOS technology has realized 512 Mbit DRAMs and 1.7 GHz clock MPUs,
and the gate length of MOSFETs in such LSIs becomes as small as 100 nm.
Figure 1.2 shows the cross sections of NMOS LSIs in the early 1970s and those of present CMOS LSIs.
The old NMOS LSI technology contains only several film layers made of Si, SiO
2
, and Al, which are
basically composed of only five elements: Si, O, Al, B, and P. Now, the structure becomes very
complicated, and so many layers and so many elements have been involved.
In the past 30 years, transistors have been miniaturized significantly. Thanks to the miniaturization,
the number of components and performance of LSIs have increased significantly. Figures 1.3 and 1.4
show the microphotographs of 1 kbit and 256 Mbit DRAM chips, respectively. Individual tiny
rectangle units barely recognized in the 16 large rectangle units of the 256 M DRAM correspond to
64 kbit DRAM. It can be said that the downsizing of the components has driven the tremendous
development of LSIs.
Figure 1.5 shows the past and future trends of the downsizing of MOSFET’s parameters and LSI chip
properties mainly used for high performance MPUs. Future trend was taken from ITRS’99 (Inter-
national Technology Roadmap for Semiconductors) [2]. In order to maintain the continuous progress of
LSIs for future, every parameter has to be shrunk continuously with almost the same rate as before.
However, it was anticipated that shrinking the parameters beyond the 0.1 mm generation would face
severe difficulties due to various kinds of expected limitations. It was expected that huge effort would be
required in research and development level in order to overcome the difficulties.
In this chapter, silicon technology from past to future is reviewed for advanced CMOS LSIs.
TABLE 1.1 Past and Current Status of Advanced LSI Products
Year Min. L
g
(mm) Ratio DRAM Ratio MPU Ratio
1970=72 10 1 1 k 1 750 k 1
2001 0.1 1=100 512 M 256,000 1.7 G 2,300

Year 2001 New Century for Solid-State Circuit
20th C
73 years since the concept of MOSFET
1928, J. Lilienfeld, MOSFET patent
54 years since the 1st transistor
1947, J. Bardeen, W. Bratten, bipolar Tr
43-42 years since the 1st Integrated Circuits
1958, J. Kilby, IC
1959, R. Noice, Planar Technology
41 years since the 1st Si-MOSFET
1960, D. Kahng, Si-MOSFET
38 years since the 1st CMOS
1963, CMOS, by F. Wanlass, C.T. Sah
31 years since the 1st 1 kbit DRAM (or LSI)
1970 Intel 1103
16 years since CMOS became the major technology
1985, Toshiba 1 Mbit CMOS DRAM
FIGURE 1.1 History of LSI in 20th century.
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1-2 Digital Design and Fabrication
1.2 Downsizing below 0.1 m m
In digital circuit applications, a MOSFET functions as a switch. Thus, complete cut-off of leakage
current in the ‘‘off’’ state, and low resistance or high current drive in the ‘‘on’’ state are required. In
addition, small capacitances are required for the switch to rapidly turn on and off. When making the
gate length small, even in the ‘‘off’’ state, the space charge region near the drain—the high potential
region near the drain—touches the source in a deeper place where the gate bias cannot control the
potential, resulting in a leakage current from source to drain via the space charge region, as shown in
Fig. 1.6. This is the well-known, short-channel effect of MOSFETs. The short-channel effect is often
measured as the threshold voltage reduction of MOSFETs when it is not severe. In order for a MOSFET
Si substrate

Field SiO
2
ILD (Interlayer
Dielectrics)
(SiO
2
+ BPSG)
Al interconnects
Passivation (PSG)
magnification
Poly Si gate
electrode
Source/Drain
Layers
Source/Drain diffusion
Gate oxide
Si substrate
Field oxide
Poly Si gate electrode
Interlayer dielectrics
Aluminum interconnects
Passivation
Materials
Si, SiO
2
BPSG
PSG
Al
Atoms
Si, O, Al,

P, B
(H, N, CI)
6 mm NMOS LSI in 1974
(a)
(b)
magnification
magnification
magnification
W via plug
W contact plug
CoSi
2
Low k ILD
Ultra-thin gate SiO
2
0.1 mm CMOS LSI in 2001
Large number of layers,
Many kinds of materials and atoms
Gate SiO
2
FIGURE 1.2 Cross-sections of (a) NMOS LSI in 1974 and (b) CMOS LSI in 2001.
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Trends and Projections for the Future of Scaling and Future Integration Trends 1-3
to work as a component of an LSI, the capability of switching-off or the suppression of the short-channel
effects is the first priority in the designing of the MOSFETs. In other words, the suppression of the short-
channel effects limits the downsizing of MOSFETs.
In the ‘‘on’’ state, reduction of the gate length is desirable because it decreases the channel resistance of
MOSFETs. However, when the channel resistance becomes as small as source and drain resistance,
further improvement in the drain current or the MOSFET performance cannot be expected. Moreover,
in the short-channel MOSFET design, the source and drain resistance often tends to even increase in

order to suppress the short-channel effects. Thus, it is important to consider ways for reducing the total
resistance of MOSFETs with keeping the suppression of the short-channel effects. The capacitances of
MOSFETs usually decreases with the downsizing, but care should be taken when the fringing portion is
FIGURE 1.3 1 kbit DRAM (TOSHIBA).
FIGURE 1.4 256 Mbit DRAM (TOSHIBA).
Vojin Oklobdzija/Digital Design and Fabrication 0200_C001 Final Proof page 4 26.9.2007 5:05pm Compositor Name: VBalamugundan
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