THE FRACTAL STRUCTURE OF DATA REFERENCE- P9 ppt
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operating separately [ 18]:
THE FRACTAL STRUCTURE OF DATA REFERENCE
(1.26)
(Note, in applying (1.26), that the processor miss ratio must be evaluated at the
single
-
reference residency time of the storage control cache).
Plugging (1.4) into (1.26), we find that, for reads, in the case <
(1.27)
Since the management of processor buffers is at the level of individual appli
-
cation records (typically one page in size), we may assume that < 0c. Thus,
the behavior of the cache under these conditions is analogous to the simpler
case when no processor buffers are present, except that a negative exponent
with a smaller absolute value, -(0c – appears in place of
Since (1.27) bears such a close resemblance to (1.4), virtually the entire line
of reasoning presented in the previous subsections extends to the case of reads
to a cache, where processor buffers are present. Corresponding to (1 .2 1), we
obtain
(1.28)
where
provided that <
What form, then, should a plot such as that presented by Figure 1.2 take,
if processor buffers are present? In the region of the plot corresponding to
(1.25) shows that the slope of the plot should be unchanged; it will
merely shift due to division by a constant. In the region < however,
the plot should show reduced responsiveness, reflecting the reduced exponent
appearing in (1.27).
Also, the transition between the two regions of the curve will reflect the
processor buffering that is being applied to the applications within the storage
pool. If no processor buffers are present, or if the processor buffer area is very
small, then we should expect to see no transition (instead, we should see a
single straight line). If processor buffering is present, but varies significantly
between individual applications, we should expect to see a gradual transition.
Hierarchical Reuse Model 27
If processor buffering is applied consistently, with the same value of τ
p
across
the entire storage pool, we should expect to see a sharp transition at the point
where the single
-
reference residency time of the cache assumes this value.
The expected performance of a cache managed at the record (rather than
track) level is similar to that just discussed, in that it is necessary to distinguish
between the two regimes τ
c
< τp and τ
c
≥ τ
p
For a record-managed cache,
however, the disparity between the two regimes will be sharper. Essentially no
hits in storage control cache should be expected for read requests with record
interarrival times shorter than τ
p
, since in this case the needed record should
always be available in a file buffer.
Taking a step back, we can now observe that, although the discussion of
the previous several paragraphs began by examining two specific levels of the
memory hierarchy, we might just as easily have been talking about any two
such levels, one of which lies immediately below the other.
In view of this
broader context, let us again review our conclusions.
Assuming that the upper of two adjacent memory levels obeys the hier
-
archical reuse model, the performance of the lower level, as a function of
single
-
reference residency time, is likely to contain a transition region. Never-
theless, the mathematical model (1.4), with suitable calibration of θ and a, can
still be used to produce a serviceable approximation of the miss ratios in the
lower memory level, awayfrom the transition region. In order for the appli
-
cation of (1.4) to be sound, there must, however, be a substantial difference in
residency times between the two levels.
In the traditional view of a memory hierarchy, the size, and hence the
residency time, of each layer increases sharply compared to the layer above
it. Within this framework, we may conclude that if (1.4) applies at any one
level of the hierarchy, it should also apply at all of the levels below. Therefore,
there is no contradiction in adopting the hierarchical reuse model as a method
of approximating data reference at all levels of a traditional memory hierarchy.
In Chapter 4, we shall argue, in some cases, for the reverse of the traditional
framework: a residency time in the processor buffer area which substantially
exceeds that in storage control cache. In such cases also, we should anticipate
that (1.4) will provide a practical model of the resulting cache performance, due
to the large difference between the cache and processor file buffer residency
times.
5.1 COMPARISON WITH EMPIRICAL DATA
Figures 1.11 through 1.20 present the actual interarrival statistics observed
at the 12 large
OS/390 installations just introduced in the previous section.
These figures largely conform to the expectations just outlined in the previous
paragraphs. The plots for the
DB2, CICS, and IMS storage pools show reduced
responsiveness at low single
-
reference residency times, and turn upward as the
28 THE FRACTAL STRUCTURE OF DATA REFERENCE
Figure 1.11.
DB2 storage pools: distribution oftrack interarrival times.
Figure 1.12. DB2 storage pools: distribution ofrecord interarrival times.
Hierarchical Reuse Model 29
Figure 1.13. CICS storage pools: distribution oftrack interarrival times.
Figure 1.14. CICS storage pools: distribution ofrecord interarrival times.
30 THE FRACTAL STRUCTURE OF DATA REFERENCE
Figure 1.15. IMS storage pools: distribution of track interarrival times.
Figure 1. 16.
IMS storage pools: distribution of record interarrival times.
