final project topic design i2c controller core

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<b>111Equation Chapter 1 Section 1</b>

<b> TRƯỜNG ĐẠI HỌC</b>

BÁCH KHOA HÀ NỘI

<b>VIỆN ĐIỆN TỬ VIỄN THÔNG</b>

--- ---<sub>  </sub>

<b>FINAL PROJECT</b>

<i><b>Topic:</b></i><b> Design I2C controller core</b>

<b>Giảng viên: TS. Võ Lê Cường</b>

Nhóm sinh viên thực hiện:

1 Vũ Huy Hoàng

201932202 Nguyễn Đức Cảnh

201932053 Lại Anh Quân

20193236

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<b>CHƯƠNG I. TÊN CHƯƠNG...4</b>

<b>CHƯƠNG II. TÊN CHƯƠNG...5</b>

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Data communication protocol, also known as data

communication control protocol, aims to ensure the efficiency andreliability of communication between two parties in a data communication network. The data communication protocol makesa series of conventions for data format, data transmission order and rate, confirmation or rejection, error detection,

retransmission control and interrogation. This report mainly introduces the Inter-Integrated Circuit (hereinafter referred to as I2C) bus communication protocol, data transmission serial SDA (hereinafter referred to as SDA) and serial SCL (hereinafter referred to as SCL).

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<b>I.Introduction to I2C</b>

I2C protocol was introduced by Phillips, which requires only two lines for communication with two or more chips and can control a network of device chips with just a two general purpose I/O pins

In embedded development, communication protocols can be divided into physical layer and protocol layer. The physical layerguarantees the transmission of data on the physical medium; the protocol layer mainly stipulates the communication logic, and uniform standards for packing and unpacking the data transmitted by both parties.

I2C protocol can also be used for communication between multiple circuit boards in equipments with or without using a shielded cable depending on the distance and speed of data transfer.

<b>I.1. Physical layer</b>

I2C is a two wire, bidirectional serial bus that provides effective data communication between two devices. I2C bus supports many devices and each device is recognized by its unique address.

I2C communication requires only two bidirectional buses, SDA and SCL. SDA is used to transmit data, and SCL is used to synchronize data transmission and reception.

Multiple I2C communication devices can be connected to the

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upper 4 bits are fixed. The device type is specified by the manufacturer. The lower 3 bits are the device pin custom address. The host is a logic module with a central processing unit CPU that initializes the data transfer of the bus and generates a clock signal that allows transmission. The host useseach device's independent address to access other devices, and any addressed device is called a slave. The I2C

communication bus supports data transfer between one host and multiple slaves, i.e. ‘one-to-many’.

Both SDA and SCL require a pull-up resistor. When the bus is idle, both lines are high level. Any device connected to the bus outputs low level will pull the bus signal low.

<b>I.2. Protocol layer</b>

The protocol layer specifies the data validity of the communication, start and stop signals, responses, data read and write sequences, address broadcasts, and so on.

<b>I.2.1. Data validity</b>

When the bus performs data transmission, each bit of datahas a corresponding clock pulse (or synchronous control), that is, each bit of data is serially transmitted bit by bit on the SDA in cooperation with SCL. While SCL is high, the data on SDA must remain stable, i.e. there must be no level changes. The high and low states on SDA are allowed to change only while SCL is low. As shown in Figure below, to transmit the first bit of data, the SDA level must be changed while SCL is still low.Then SCL is high, the slave receives the first bit of data. SDA can change according to the transmission data value when SCL goes low. when SCL is high again, SDA can't change level, slavereceives second bit data, and so on, until reaches stop signal.

<b>I.2.2. Start and stop signals</b>

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The I2C bus is said to be idle when both SCL and SDA are at logic 1 level. When the master (controller) wishes to transmitdata to a slave, it begins by issuing a start sequence on the I2Cbus, which is a high to low transition on the SDA line while the SCL line is high.

The bus is considered to be busy after the START condition. After the START condition, slave address is sent by the master. The slave device whose address matches the address that is being sent out by the master will respond with an acknowledgement bit on the SDA line by pulling the SDA linelow. Data is transferred in sequences of 8 bits. The bits are placed on the SDA line starting with the MSB (Most Significant Bit). For every 8 bits transferred, the slave device receiving the data sends back an acknowledge bit, so there are actually 9 SCL clock pulses to transfer each 8 bit byte of data.

If the receiving device sends back a low ACK bit, then it has received the data and is ready to accept another byte. If it sends back a high then it is indicating it cannot accept any further data and the master should terminate the transfer by sending a STOP sequence. The SDA line is driven low while SCL line is high. This signals the end of the transaction with the slave device.

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<b>I.2.3. I2C read and write processa) Write data flow</b>

The standard process for writing data is:

(1) The host first initiates the START signal; then sends the I2C address code (7bit) and write operation 0 (1bit), waiting for the slave to respond to the ACK. This process is called address broadcast.

(2) The slave sends an ACK;

(3) The host sends the register address (8bit), that is, the data is written to the slave, waiting for the slave to respond to the ACK;

(4) The slave sends an ACK;

(5) The host sends data (8 bits), that is, the data to be written into the register, waiting for the slave to respond to the ACK;(6) The slave sends an ACK;

(7) Steps 5 and 6 can be repeated multiple times, that is, sequentially writing a plurality of registers starting from the register address indicated in step 3

(8) The host sends a stop signal.

The standard process for reading the data is :

(1) The host first initiates a START signal; then sends an I2C address code (7bit) and a write operation 0 (1bit), waiting for

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the slave to respond to the ACK;(2) The slave sends an ACK;

(3) The host sends the register address (8bit), that is, the data to be read is stored in the slave position, waiting for the slave to respond to the ACK;

(4) The slave sends an ACK;

(5) The host initiates the START signal again; sends the I2C address code (7bit) and read operation 1 (1bit), prepares to read the data, and waits for the slave to respond to the ACK;(6) The slave sends an ACK;

(7) At this time, the slave transmits data from the previously received address, and the host receives (8 bits);

(8) The host sends a NACK;

(9) Steps 7 and 8 may be repeated many times, and the slave sequentially issues a number of sets of data starting from the register address indicated by step 3. Note that each time the host receives 1 Byte of data, it must send an ACK to the slave so that the slave can continue to send data, except for the last 1 Byte. (10) The host sends a stop signal

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<b>II. Design Module</b>

<b>II.1. System modeling</b>

The Prescale Register (address = 0x00 and 0x01) is used toprescale the scl clock line based on the master clock. Since thedesign is driven by a (5 x scl frequency) internally, the prescaleregister is programmed according to the equation [master clockfrequency / (5 x (sclk frequency)) - 1]. The content of this registercan only be modified when the core is not enabled.

Only two bits of the Control Register (address = 0x01) are usedfor this design. The MSB of this register is the most critical onebecause it enables or disables the entire I2 C core. The core will notrespond to any command unless this bit is set.

The Transmit Register and the Receive Register share the sameaddress (address = 0x30) depending on the direction of datatransfer. The data to be transmitted via I2 C will be stored in theTransmit Register, while the byte received via I2 C is available in theReceive register.

The Status Register and the Command Register share the sameaddress (address = 0x04). The Status Register allows the monitoringof the I2 C operations, while the Command Register stores the nextcommand for the next I2 C operation. Unlike the rest of the

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registers, the bits in the Command Register are clearedautomatically after each operation. Therefore this register has to bewritten for each start, write, read, or stop of the I2 C operation. Table3 provides a detailed description of each bit in the internal registers.

<b>Input/output signals</b>

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<b>External connections </b>

<b>Registers list</b>

<b>Control register </b>

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<b>Transmit register </b>

<b>Receive register</b>

<b>Command register</b>

<b>Status register </b>

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There are the following states:

1. State 0 = IDLE (reset =1, initiate =1) Else when reset =0 and initiate =0 then the following states appear.

2. State 1 = START CONDITION - SDA is pulled from high to low whenSCL is still high

3. State 2= SLAVE ADDRESS – Normal mode so, 7-bit slave address is sent.

4. State 3= READ/WRITE BIT- Write is 0 and Read is 1.

5. State 4 = ACK/NACK BIT- SDA line is low if acknowledged and SDA line is high if NACK (not acknowledged)

6. State 5 = DATA- 8-bit data is sent or received at once

7. State 6 = ACK_1 BIT – After receiving the data ACK bit sent i.e. SDA line is pulled low. NACK bit means SDA line is high

8. State 7 = STOP CONDITION- Master will terminate the

communication by pulling the SDA line from low to high when SCL line is still high.

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<b>Byte Command Controller Module: </b>

The microcontroller issues commands and data through the WISHBONE interface in byte format. The information is fed into the Byte Command Controller module and is translated into I2 C sequences required for a byte transfer. This module includes a state machine to handle normal I2 C transfer sequences. The module thenbreaks up a single command into multiple clock cycles for the Bit Command Controller to work on bit-level I2 C operations. This module also contains a shift register which is used for both READ and WRITE cycles. During a READ cycle, the input to the shift register comes from the sda line. After eight scl cycles, the shifted-indata is copied into the Receive Register. During a WRITE cycle, the input to the shift register comes from the WISHBONE data bus. The data in the shift register is shifted out to the sda line during WRITE.

<b>Bit Command Controller Module</b>

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This module directly controls the I2 C bus, scl and sda lines, by generating the correct sequences for START, STOP, Repeated START, READ, and WRITE commands. Each bit operation is divided into five (5 x scl frequency) clock cycles (idle, A, B, C, and D), except for the START command that has six clock cycles. This ensures that the logical relationship between the scl and sda lines meets the I2 C requirement for these critical commands. The internal clock running at 5 x scl frequency is used for the registers in this module.

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<b>I2C Master core with interface</b>

The first one would be the I2C_bit_control module with above inputs and

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Generate bus status controllers

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Detect start and stop condition

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Generate busy signal

Generate arbitration lost signal

Finally: generate statemachine  I2C_Byte_control module

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 i2c_master_top.v to gathered all the module

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<b>2. Create interfacing with Wishbone and Phillips I2C The Wishbone master module has:</b>

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<b>II.2. Verify design</b>

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<b>Conclusion</b>

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<b>TÀI LIỆU THAM KHẢO</b>

[1] Tài liệu[2] Tài liệu[3] Tài liệu

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