Z80 is VI XỬ LÝ
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Z80
Instruction Set
:
Structure of Instructions
Every instruction consists of an operational Code (OP-Code)
and -if necessary- an address part for the operand(s).
OP-Code
Address(es)
Operand(s)
0
1
2
3
Z80:
OP-Code 1 Byte (exceptions: in OPs using index
registers
the OP-Code is two bytes)
the instruction set is not orthogonal
R1 op R2
(A) op R
(A1) op (A2)
(A1) op (A2)
R3
R
R
(A3)
f A, op: binary operation, : transfer, A: address, R: register
Z80 Address Modes (1)
Implied
The instruction has only an OP-Code, the register is "implied"
in the code
Ex: CPL (Complement A): A ¬ A, OP-Code 2FH
Register Direct
The Instruction has only an OP-Code, both source and destination
registers are defined in this code
Ex: LD A,B (Load A with contents of B): A B, OP-Code 78H
Register Indirect
The instruction has only the OP-Code, the destination register is
defined in this code and a 16Bit register containing the address of
the source operand
Ex: LD A,(HL) (Load A from address contained in HL): A (HL), 7EH
Z80 Address Modes (2)
Immediate
The instruction contains the value of the operand immediately
eg LD BC,1000H: BC 1000H, Op-Code 01H 00H 10H
eg LD A,1FH: A 1FH, Op-Code 3EH 1FH
OP-Code
OP-Code
n
m
m
8-bit operand m
16-bit operand {m,n}
Extended (Direct)
The address of the operad is given
as part of the instruction
eg LD A,(1000H): A (1000H),
OP-Code 3AH 00H 10H
OP-Code
memory
...
n
m
m
address
n
operand
...
Z80 Address Modes (3)
OP-Code
offset
Relative
The address is relative to PC
(only for Branches!)
eg JR 10H: PC PC + 10H
Op-Code 18H 0EH
PC
next OP-Code
Hint for JR e:
memory
...
PC
OP-Code (JR)
PC+2
x=e-2
next instruction
...
destination address:
(PC + 2) + x = PC + e
-126
0
e=x+2
x: (-128, +127)
e: (-126, +129)
+129
Z80 Address Modes (4)
Indexed
The address of the operand is constructed from the index
register
(all instructions with index registers have 2 byte OP-Codes!)
eg LD A,(IX + 10H): A (IX + 10H,) Code DDH 7EH 10H
operand
OP-Code1
OP-Code2
dislpacement d
sign extended d
d: signed 8-bit (-128, +127)
IX or IY
...
operand
...
Z80 Address Modes (5)
Modified Page Zero
A fixed address correspondence only used for the restart instruction
eg RST 20H: Stack PC, PCH 00H, PCL 20H,
OP-Code E7H
RST p: Opcode 11 t 111 B with:
Bit
t
p
t
p
000
00H
100
20H
001
08H
101
28H
010
10H
110
30H
011
18H
111
38H
Direct addressing of a bit for bit manipulations
eg SET 3,A (Set bit 3 of A to 1): A3 1, OP-Code CBH DFH
(SET b,A: Ab 1, OP-Code CBH 11 b 111B)
Z80 Address Modes (6)
I/O Addressing
Only with special I/O commands (IOREQ = 1, MREQ = 0)
Ex: IN A,(10H): A (n), OP-Code DBH 10H
Hint (A7, ..., A0) n and (A15, ..., A8) A
By loading A before using an I/O instruction the available
space for I/O-addresses can be extended
Sample Line from Instruction Set
Listing
Mnemonic
ADD A,(HL)
IN A,(n)
...
Symbolic
Operation
A A+(HL)
A (n)
Flags
S Z
H
P/V N C
X X V
0
• • X • X
•
• •
# of Bytes
1
2
# of M Cycles
2
3
Opcode
76 543
210
10 000
110
11 011
011
n
# of T states
7
11
Hex
86
DB
...
Comments
n to A0 A7
Acc. to A8 A15
Instruction Classes
•
•
•
•
•
•
•
Data Transfer Group
Arithmetic Group
Logical and Rotate Group
Branch Group
Stack, I/O, and Machine Contol Group
Exchange, Block Transfer, and Search Group
Bit Manipulation Group
Data Transfer Group
OP Code
Hex
Mnemonic
78
21 00 07
LD A,B
LD HL,0700H
Symbolic
Operation
Description
AB
place a copy of B in A
HL 0700H load HL with 0700H
load IX with the
contents of memory
DD 2A 00 07 LD IX,(0700H) IX (0700H)
starting at location
0700H *
*
Low Address (0700H) = Least Significant Byte (LSB)
High Address (0701H) = Most Signifikant Byte (MSB)
Arithmetic Group
OP Code
Hex
80
09
Mnemonic
Symbolic
Operation
Description
B is added to A,
ADD A,B
AA+B
result in A
BC is added to HL,
ADD HL,BC HL HL + BC
result in HL
Logic and Rotate Group
OP Code
Symbolic
Mnemonic
Hex
Operation
A0
AND B
BE
CP (HL)
Description
Bitwise AND-operation of
A A · B A and B,
result in A
the contents of the
memory location
A - (HL) addressed by HL is
subtracted from A,
set flags, A unchanged
OP Code
Hex
C3 00 01
30 (e-2)
CD 00 01
C9
Branch
Group
Symbolic
Mnemonic
Operation
Description
PC 0100H
control is tranferred to
address 0100H
JR NC,0100H
PC PC + e
control is transferred to
address in PC + offset e
if Carry-Flag is 0
CALL 0100H
(SP-1) PCh *
(SP-2) PCl *
PC 0100H
SP SP - 2
control is transferred to
subroutine at address
0100H, return address is
stored on stack, SP is
decremented by 2
RET
PCl (SP) *
PCh (SP+1) *
SP SP + 2
control is transferred to
address on top of stack
(return address), SP is
incremented by 2
JP 0100H
*
PCh/l: high/low order byte of PC
Stack, I/O, and Machine Control Group
OP Code
Hex
Mnemonic
C5
PUSH BC
C1
POP BC
Symbolic
Operation
(SP-1) B
(SP-2) C
SP SP - 2
C (SP)
B (SP+1)
SP SP + 2
Description
BC is copied to top of
stack, SP is decremented
by 2
top of stack is copied to
BC, SP is incremented by 2
Exchange, Block Transfer, and
Search Group
OP Code
Hex
Mnemonic
D9
EXX
ED B8
LDDR
ED A1
CPI
Symbolic
Operation
BC B'C'
DE D'E'
HL H'L'
(DE) (HL)
DE DE - 1
HL HL - 1
BC BC - 1
A - (HL)
HL HL + 1
BC BC - 1
Description
exchange of primary and
alternative general purpose
registers
load location (DE) with
location (HL), decrement
DE, HL, and BC,
repeat until BC = 0
compare location (HL) with
accumulator, increment HL,
decrement BC,
set flags, A unchanged
Bit Manipulation Group
OP Code
Hex
Mnemonic
CB 61
CB 74
BIT 4,C
SET 6,H
CB 97
RES 6,H
*
Symbolic
Operation
Z ¬C4 *
Description
H6 1 *
test bit 4 of C, set Z flag
set bit 6 of H to 1
H6 0 *
set bit 6 of H to 0
the Index at the register denotes the bitpostion in that register
