EX.NO:1(a) Design and Simulation of Half Adder using VHDL
AIM:
To design and verify the Half Adder using VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
THEORY:
Let's start by adding two binary bits. Since each bit has only two
possible values, 0 or 1, there are only four possible combinations
of inputs. These four possibilities, and the resulting sums, are:
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10
That fourth line indicates that we have to account for two output bits
when we add two input bits: the sum and a possible carry. Let's set this
up as a truth table with two inputs
VHDL CODING:
library ieee;
use ieee.std_logic_1164.all;
entity halfadder is
port (a,b:in bit;
sum,carry: out bit);
end halfadder;
architecture arch_halfadder of halfadder is
begin
sum<= a xor b;
carry<= a and b;
end arch_halfadder;
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PROCEDURE

1. Open new file in VHDL source editor
2. Type the VHDL coding for Half Adder in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values.
RESULT:
Thus the Half adder is designed and verified using VHDL.
EX.NO:1(b) Design and Simulation of Full Adder using VHDL
AIM:
To design and verify the Full Adder using VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
THEORY:
To construct a full adder circuit, we'll need three inputs and two
outputs. Since we'll have both an input carry and an output carry, we'll
designate them as C
IN
and C
OUT
. At the same time, we'll use S to
designate the final Sum output. The resulting truth table is shown to
the right.
VHDL CODING:
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (x, y, Cin: in bit;
Cout,S :out bit);
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end fulladder;
architecture arch_fulladder of fulladder is
begin
S<= (x xor y) xor Cin;
Cout<= (x and y) or (y and Cin) or (Cin and x);
end arch_fulladder;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for Full Adder in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
Thus the Full adder is designed and verified using VHDL.
EX.NO:2(a) Design and Simulation of 4:2 Encoder using VHDL
AIM:
To design and verify the 4:2 Encoder using VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
Theory:
The encoder is a combinational circuit that performs the reverse operation
of the decoder. The encoder has a maximum of 2
n
inputs and n outputs. An
encoder performs the opposite function of a decoder. An encoder takes a
input on one of its 2n input lines and converts it to a coded output with n
lines.
VHDL CODING:

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library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (a,b,c,d:in bit;
y:out bit_vector(1 downto 0));
end encoder;
architecture arch_encoder of encoder is
begin
process (a,b,c,d)
begin
if (a='1')then
y<="00";
elsif (b='1')then
y<="01";
elsif (c='1')then
y<="10";
elsif (d='1')then
y<="11";
end if;
end process;
end arch_encoder;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for 4:2 Encoder in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

RESULT:
Thus the 4:2 Encoder is designed and verified using VHDL.
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EX.NO:2(b) Design and Simulation of 2:4 Decoder using VHDL
AIM:
To design and verify the 2:4 Decoder using VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
Theory:
The basic function of a decoder is to detect the presence of a particular
combination of bits at the inputs and indicate the presence of that particular
set of bits by outputting a specified output level. Typically a decoder with
n input lines requires 2n output lines to decode every possible combination
of bits. BCD to decimal conversion, looked at in part3 of this lab, is
accomplished using a decoder which has 4 input lines and 10 output lines
(the 10 output lines correspond to the decimal numbers 0-9). This device is
used to convert between binary numbers and decimal numbers
VHDL CODING:
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port (a,b:in bit;
y:out bit_vector(3 downto 0));
end decoder;
architecture arch_decoder of decoder is
begin
process (a,b)
begin
if (a='0' and b='0' )then

y<="0001";
elsif (a='0' and b='1' )then
y<="0010";
elsif (a='1' and b='0' )then
y<="0100";
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elsif (a='1' and b='1' )then
y<="1000";
end if;
end process;
end arch_decoder;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for 2:4 Decoders in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
Thus the 2:4 Decoder is designed and verified using VHDL.
EX.NO:3(a) Design and Simulation of 8:1 Multiplexer using
VHDL
AIM:
To design and verify the 8:1 Multiplexer using VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
THEORY:
A multiplexer or MUX is a device that allows digital information
from several different sources on different input lines to be routed onto a

single line. A basic MUX has several input lines, several data select lines
or control signals and one output signal. The input that gets selected to
pass to the output is determined by the control signals.
VHDL CODING:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux8to1 is
port(y:out std_logic;
s:in std_logic_vector(2 downto 0);
i:in std_logic_vector(0 to 7));
end mux8to1;
architecture arch_mux8to1 of mux8to1 is
begin
process(s,i)
begin
case s is
when "000" => y <=i(0);
when "001" => y <=i(1);
when "010" => y <=i(2);
when "011" => y <=i(3);
when "100" => y <=i(4);
when "101" => y <=i(5);
when "110" => y <=i(6);
when "111" => y <=i(7);
when others =>null;
end case;
end process;

end arch_mux8to1;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for 8:1 Multiplexer in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
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RESULT:
Thus the 8:1 Multiplexer is designed and verified using VHDL.
EX.NO:3(b) Design and Simulation of 1:8 Demultiplexer using
VHDL
AIM:
To design and verify the 1:8 Demultiplexer using VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
THEORY:
A demultiplexer is the opposite of a multiplexer. In electronic devices,
demultiplexer is a logical circuit which takes a single input and sends
out this input to one of several outputs available. During this process
the output that has been selected is assigned the value 1, while the
other outputs are assigned the value 0. The definition is slightly
different when we are talking about demultiplexers in the context of
networking. In the networking context, a demultiplexer is a device
that receives multiple signals that have been transmitted on one line
and then decodes these single line signals into separate multiple
signals. A demultiplexer is usually always used in tandem with a
multiplexer. Demultiplexers can be analog demultiplexers or digital

demultiplexers. Digital demultiplexers generally function as decoders.
VHDL CODING:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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entity demux1to8 is
port(y:out std_logic_vector(0 to 7);
s:in std_logic_vector(2 downto 0);
i:in std_logic);
end demux1to8;
architecture arch_demux1to8 of demux1to8 is
begin
process(s,i)
begin
case s is
when "000" => y(0)<=i;
when "001" => y(1)<=i;
when "010" => y(2)<=i;
when "011" => y(3)<=i;
when "100" => y(4)<=i;
when "101" => y(5)<=i;
when "110" => y(6)<=i;
when "111" => y(7)<=i;
when others =>null;
end case;
end process;
end arch_demux1to8;
PROCEDURE

1. Open new file in VHDL source editor
2. Type the VHDL coding for 1:8 Demultiplexers in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
Thus the 1:8 Demultiplixer is designed and verified using VHDL.
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EX.NO:4 Design and Simulation of 4x4 Multiplier using VHDL
AIM:
To design and verify the 4X4 Array Multiplier using VHDL.
TOOLS REQUIRED:
1.Computer with ModelSim Software
THEORY
The simple serial by parallel booth multiplier is particularly well
suited for bit serial processors implemented in FPGAs without carry chains
because all of its routing is to nearest neighbors with the exception of the
input. The serial input must be sign extended to a length equal to the sum
of the lengths of the serial input and parallel input to avoid overflow,
which means this multiplier takes more clocks to complete than the scaling
accumulator version.
VHDL CODING:
// 4X4 Array Multiplier
library ieee;
use ieee.std_logic_1164.all;
entity a1 is
port(a,b:in std_logic;c:out std_logic);
end a1;

architecture a of a1 is
begin
c <= a and b;
end a;
library ieee;
use ieee.std_logic_1164.all;
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entity fa is
port(a,b,c:in std_logic;s,ca:out std_logic);
end fa;
architecture fa1 of fa is
begin
ca <= (a and b) or ( b and c) or ( a and c);
s <= a xor b xor c;
end fa1;
library ieee;
use ieee.std_logic_1164.all;
entity mul is
port(a,b:in std_logic_vector(3 downto 0);
p:out std_logic_vector(7 downto 0));
end mul;
architecture multiplier of mul is
component a1
port(a,b:in std_logic;c:out std_logic);
end component;
component fa
port(a,b,c:in std_logic;s,ca:out std_logic);
end component;
signal c :std_logic_vector(15 downto 0);

signal s:std_logic_vector(15 downto 0);
signal q :std_logic_vector(15 downto 0);
signal z : std_logic := '0';
begin
a0: a1 port map(a(0),b(0),p(0));
a2: a1 port map(a(1),b(0),c(1));
a3: a1 port map(a(2),b(0),c(2));
a4: a1 port map(a(3),b(0),c(3));
a5: a1 port map(a(0),b(1),c(4));
a6: a1 port map(a(1),b(1),c(5));
a7: a1 port map(a(2),b(1),c(6));
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a8: a1 port map(a(3),b(1),c(7));
a9: a1 port map(a(0),b(2),c(8));
a10: a1 port map(a(1),b(2),c(9));
a11: a1 port map(a(2),b(2),c(10));
a12: a1 port map(a(3),b(2),c(11));
a13: a1 port map(a(0),b(3),c(12));
a14: a1 port map(a(1),b(3),c(13));
a15: a1 port map(a(2),b(3),c(14));
a16: a1 port map(a(3),b(3),c(15));
f0:fa port map(c(1),c(4),z,p(1),q(0));
f1:fa port map(q(0),c(2),c(5),s(1),q(1));
f2:fa port map(q(1),c(3),c(6),s(2),q(2));
f3:fa port map(q(2),z,c(7),s(3),q(3));
f4:fa port map(s(1),z,c(8),p(2),q(4));
f5:fa port map(q(4),s(2),c(9),s(4),q(5));
f6:fa port map(q(5),s(3),c(10),s(5),q(6));
f7:fa port map(q(6),q(3),c(11),s(6),q(7));

f8:fa port map(s(4),z,c(12),p(3),q(8));
f9:fa port map(q(8),s(5),c(13),p(4),q(9));
f10:fa port map(q(9),s(6),c(14),p(5),q(10));
f11:fa port map(q(10),q(7),c(15),p(6),p(7));
end multiplier;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for multiplier in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
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Thus the 4X4 Array Multiplier Half adder is designed and verified
using VHDL.
EX.NO:5(a) Design and Simulation of JK Flip Flop using VHDL
AIM:
To design and verify the JK Flipflop using VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
THEORY:
The JK flip-flop behaves just like the RS flip-flop. The Q and Q'
outputs will only change state on the falling edge of the CLK signal, and
the J and K inputs will control the future output state pretty much as
before. However, there are some important differences.
If both the J and K inputs are held at logic 1 and the CLK signal continues
to change, the Q and Q' outputs will simply change state with each falling
edge of the CLK signal. (The master latch circuit will change state with

each rising edge of CLK.) We can use this characteristic to advantage in a
number of ways. A flip-flop built specifically to operate this way is
typically designated as a T (for Toggle) flip-flop. The lone T input is in fact
the CLK input for other types of flip-flops.
VHDL CODING:
// JK Flipflop
library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port (j,k,clk:in std_logic;
q,qb:inout std_logic);
end jkff;
architecture arch_jkff of jkff is
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begin
process (j,k,clk)
begin
if (rising_edge(clk))then
if (j='0' and k='0')then
q<=q; qb<=qb;
elsif (j='0' and k='1')then
q<=’0’;qb<=’1’;
elsif (j='1' and k='0')then
q<=’1’;
qb<=’0’;
elsif (k='1' and k='1')then
q<= not q; qb<= not qb;
end if;
end if;

end process;
end arch_jkff;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for JK Flip Flop in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
Thus the JK flip-flop is designed and verified using VHDL.
EX.NO:5(b) Design and Simulation of D Flip Flop using VHDL
AIM:
To design and verify the D Flipflop using VHDL.
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TOOLS REQUIRED:
1.Computer with ModelSim Software
THEORY:
The edge-triggered D flip-flop is easily derived from its RS counterpart.
The only requirement is to replace the R input with an inverted version of
the S input, which thereby becomes D. This is only needed in the master
latch section; the slave remains unchanged.
One essential point about the D flip-flop is that when the clock input falls
to logic 0 and the outputs can change state, the Q output always takes on
the state of the D input at the moment of the clock edge. This was not true
of the RS and JK flip-flops. The RS master section would repeatedly
change states to match the input signals while the clock line is logic 1, and
the Q output would reflect whichever input most recently received an
active signal. The JK master section would receive and hold an input to tell

it to change state, and never change that state until the next cycle of the
clock. This behavior is not possible with a D flip-flop
VHDL CODING:
// D Flipflop
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (d,clk:in std_logic;
q:out std_logic);
end dff;
architecture arch_dff of dff is
begin
process (d,clk)
begin
if(rising_edge(clk) )then
q<=d;
end if;
end process;
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end arch_dff;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for D Flip Flop in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
Thus the D flip-flop is designed and verified using VHDL.

EX.NO:6(a) Design and Simulation of 4 bit UP Counter using
VHDL

AIM:
To design and verify the Up counter using VHDL.
TOOLS REQUIRED:
1.Computer with ModelSim Software
THEORY:
The result is a four-bit synchronous "up" counter. Each of the higher-
order flip-flops are made ready to toggle (both J and K inputs "high") if the
Q outputs of all previous flip-flops are "high." Otherwise, the J and K
inputs for that flip-flop will both be "low," placing it into the "latch" mode
where it will maintain its present output state at the next clock pulse.
Since the first (LSB) flip-flop needs to toggle at every clock pulse, its
J and K inputs are connected to Vcc or Vdd, where they will be "high" all
the time. The next flip-flop need only "recognize" that the first flip-flop's Q
output is high to be made ready to toggle, so no AND gate is needed.
However, the remaining flip-flops should be made ready to toggle only
when all lower-order output bits are "high," thus the need for AND gates.
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VHDL CODING:
// up Counters
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity counter is port(clk, rst : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is

signal tmp: std_logic_vector(3 downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
tmp <= "0000";
elsif (clk'event and clk='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for Up Counter in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
Thus the 4 bit up counter is designed and verified using VHDL.
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EX.NO:6(b) Design and Simulation of 4 bit DOWN Counter using
VHDL
AIM:
To design and verify the Down counter using VHDL.
TOOLS REQUIRED:
1.Computer with ModelSim Software
THEORY:

To make a synchronous "down" counter, we need to build the circuit
to recognize the appropriate bit patterns predicting each toggle state
while counting down. Not surprisingly, when we examine the four-bit
binary count sequence, we see that all preceding bits are "low" prior to
a toggle (following the sequence from bottom to top.
VHDL CODING:
// Down Counters
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity counter is port(clk, rst : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
tmp <= "0000";
elsif (clk'event and clk='1') then
tmp <= tmp - 1;
end if;
end process;
Q <= tmp;
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end archi;
PROCEDURE
1. Open new file in VHDL source editor

2. Type the VHDL coding for Down Counter in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
Thus the 4 bit down counter is designed and verified using VHDL.
EX.NO:7(a) Design and Simulation of SISO Shift Register using
VHDL
AIM:
To design and verify the Serial in Serial out Shift Registers using
VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
THEORY:
Serial-in, serial-out shift registers delay data by one clock time for each
stage. They will store a bit of data for each register. A serial-in, serial-out
shift register may be one to 64 bits in length, longer if registers or packages
are cascaded. Below is a single stage shift register receiving data which is
not synchronized to the register clock. The "data in" at the D pin of the
type D FF (Flip-Flop) does not change levels when the clock changes for
low to high. We may want to synchronize the data to a system wide clock
in a circuit board to improve the reliability of a digital logic circuit.
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VHDL CODING:
// Serial In Serial Out
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity siso is
port(di,clk,rst:in std_logic;
dout:out std_logic);
end siso;
architecture arch_siso of siso is
signal s:std_logic_vector(0 to 6);
begin
process(di,clk,rst)
begin
if(rst='1')then
dout<='0';
elsif(clk'event and clk='1')then
s(0)<=di;
s(1)<=s(0);
s(2)<=s(1);
s(3)<=s(2);
s(4)<=s(3);
s(5)<=s(4);
s(6)<=s(5);
dout<=s(6);
end if;
end process;
end arch_siso;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for Serial In Serial Out shift Register in the
new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
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5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
Thus Serial in Serial out Shift Registers is designed and verified using
VHDL.
EX.NO:7(b) Design and Simulation of SIPO Shift Register using
VHDL
AIM:
To design and verify the Serial In Parallel Out Shift Register using
VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
THEORY:
A serial-in/parallel-out shift register is similar to the serial-in/ serial-
out shift register in that it shifts data into internal storage elements and
shifts data out at the serial-out, data-out, pin.
It is different in that it makes all the internal stages available as
outputs. Therefore, a serial-in/parallel-out shift register converts data from
serial format to parallel format. If four data bits are shifted in by four
clock pulses via a single wire at data-in, below, the data becomes available
simultaneously on the four Outputs QA to QD after the fourth clock pulse.
VHDL CODING:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sipo_new is
port(di,clk,rst:in std_logic;
dout:out std_logic_vector(0 to 7));
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end sipo_new;
architecture arch_sipo of sipo_new is
signal s:std_logic_vector(0 to 7);
begin
process(di,clk,rst)
begin
if(rst='1')then
dout<="00000000";
elsif(clk'event and clk='1')then
s(0)<=di;
s(1)<=s(0);
s(2)<=s(1);
s(3)<=s(2);
s(4)<=s(3);
s(5)<=s(4);
s(6)<=s(5);
s(7)<=s(6);
dout(0)<=s(0);
dout(1)<=s(1);
dout(2)<=s(2);
dout(3)<=s(3);
dout(4)<=s(4);
dout(5)<=s(5);
dout(6)<=s(6);
dout(7)<=s(7);
end if;
end process;
end arch_sipo;
PROCEDURE

1. Open new file in VHDL source editor
2. Type the VHDL coding for Serial In Parallel Out Shift Register in the
new file.
3. Save the file with the extension of .vhd
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4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:
Thus Serial in Parallel out Shift Register is designed and verified
using VHDL.
EX.NO:8 Design and Simulation of Frequency Divider using
VHDL
AIM:
To design and verify the Frequency Divider using VHDL.
TOOLS REQUIRED:
1. Computer with ModelSim Software
THEORY:
A frequency divider is an electronic circuit that takes an input signal with a
frequency, f
in
, and generates an output signal with a frequency:
where n is an integer. Phase-locked loop frequency synthesizers make use
of frequency dividers to generate a frequency that is a multiple of a
reference frequency. Frequency dividers can be implemented for both
analog and digital applications.
VHDL CODING:
library ieee;
use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;
entity freqdiv is port(clk, rst : in std_logic;
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clkby2,clkby4,clkby8,clkby16:out std_logic);
end freqdiv;
architecture archi of freqdiv is
signal Q: std_logic_vector(3 downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
Q <= "0000";
elsif (clk'event and clk='1') then
Q <= Q + 1;
end if;
end process;
clkby2<=Q(0);
clkby4<=Q(1);
clkby8<=Q(2);
clkby16<=Q(3);
end archi;
PROCEDURE
1. Open new file in VHDL source editor
2. Type the VHDL coding for Frequency Divider in the new file.
3. Save the file with the extension of .vhd
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values
RESULT:

Thus the Frequency Divider is designed and verified using VHDL.
EX.NO:9 CMOS INVERTER
AIM:
To design and verify the CMOS inverter using SPICE
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TOOLS REQUIRED:
1. WinSpice3
2. Computer
PROCEDURE:
1. Open a notepad file
2. Write a program for CMOS inverter.
3. Specify the input and output
4. Save the file with the extension of .cir
5. Open the Winspice software
6. Click the file and open the Program file
7. Verify the input and output plots
WINSPICE PROGRAM:
M1 3 2 1 1 p L=2u w=3u
M2 3 2 0 0 n L=2u w=3u
vdd 1 0 dc 5v
vin 2 0 pulse(0 5 0 1n 1n 10n 50n)
.plot tran v(2)
.plot tran v(3)
.tran 1n 100n
.model p pmos
.model n nmos
.end
RESULT:


Thus CMOS Inverter is designed and verified using SPICE
EX.NO:10(A) CMOS NAND GATE
AIM:
To design and verify the CMOS NAND gate using SPICE
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