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Điện tử số part 1

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Digital Electronics
Digital Electronics
Dr. Pham Ngoc Nam
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/2
Acknowledgement
Acknowledgement

The main part of the slides was adopted and modified from the original slides of Prof.
Rudy Lauwereins, Vice president of IMEC, Leuven, Belgium with his permission.
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential


circuits
FSMD
design
VHDL
Your instructor

Bộ môn kỹ thuật điện tử tin học

Office: C9-401

Email: ,

Course email: />•
Research:

FPGA, hệ nhúng

Trí tuệ nhân tạo

Embedded Systems and Reconfigurable Computing Lab

Education:

K37 điện tử-ĐHBK Hà nội (1997)

Master về trí tuệ nhân tạo 1999, Đại học K.U. Leuven, vương quốc Bỉ

Đề tài: Nhận dạng chữ viết tay

Tiến sỹ kỹ thuật chuyên ngành điện tử-tin học, 9/ 2004, Đại học K.U.

Leuven-IMEC, Vương Quốc Bỉ

Đề tài: quản lý chất lượng dịch vụ trong các ứng dụng đa
phương tiện tiên tiến
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/4
Course contents
Course contents

Digital design

Combinatorial circuits: without status

Sequential circuits: with status

FSMD design: hardwired processors

Language based HW design: VHDL

©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/5
Course contents
Course contents

Digital design

Combinatorial circuits: without status

Sequential circuits: with status

FSMD design: hardwired processors

Language based HW design: VHDL
©
R.Lauwereins
Imec 2001
Digital

design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/6
Contents of “Digital Design”
Contents of “Digital Design”

Introduction to the course

Data representation

Boolean algebra

Logical gates
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits

FSMD
design
VHDL
1/7
Contents of “Digital Design”
Contents of “Digital Design”

Introduction to the course

Course book

Goal

Exercises and laboratory sessions

Exam

Data representation

Boolean algebra

Logical gates
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits

Sequential
circuits
FSMD
design
VHDL
1/8
Contents of “Digital Design”
Contents of “Digital Design”

Introduction to the course

Course book

Goal

Exercises and laboratory sessions

Exam

Data representation

Boolean algebra

Logical gates
©
R.Lauwereins
Imec 2001
Digital
design
Combina-

torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/9
Course books
Course books

Mandatory:

“Principles of Digital Design”, Daniel D. Gajski,
Prentice Hall, 1997, ISBN 0-13-301144-5

References:

Douglas L. Perry, VHDL: Programming by Examples, McGraw-
Hill, fourth Edition, 2002.

“Logic and Computer Design Fundamentals”, M. Morris Mano
& Charles R. Kime, Prentice Hall, 2nd edition, 2000, ISBN 0-
13-016176-4

TS. Nguyễn Nam Quân : “Toán logic và Kỹ thuật số”, Nhà
xuất bản khoa học và kỹ thuật, 2006
©
R.Lauwereins
Imec 2001

Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/10
Contents of “Digital Design”
Contents of “Digital Design”

Introduction to the course

Course book

Goal

Exercises and laboratory sessions

Exam

Data representation

Boolean algebra

Logical gates
©

R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/11
Goal of the course
Goal of the course

Give insight in the design of digital electronic systems at the gate and register-transfer
level

Teach the use of modern design tools

Offer all building blocks needed to construct complex digital circuits, including
processors

Present the difference between functional requirements (operation) and non-functional
requirements (cost, speed, power, area)

Introduce modern implementation platforms: PLA, PLD, FPGA
©
R.Lauwereins

Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/12
Contents of “Digital Design”
Contents of “Digital Design”

Introduction to the course

Course book

Goal

Exercises and laboratory sessions

Exam

Data representation

Boolean algebra

Logical gates

©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/13
Exercises and laboratory sessions
Exercises and laboratory sessions

Bài 1: Các phần tử logic cơ bản – Bộ chọn dữ liệu phân kênh

Bài 2: Các Trigơ RS, D, JK – Bộ đếm LED 7 thanh

Bài 3: Làm quen với phần mềm thí nghiệm thông qua một ví dụ thiết kế đơn giản

Bài 4: Thiết kế bộ so sánh hai số 3 bit: Bài thí nghiệm này giúp sinh viên luyện tập tối thiểu hóa bìa
Karnaugh 6 biến và biết cách thiết kế mạch logic tổ hợp từ các phần tử logic cơ bản

Bài 5: Thiết kế bộ phát hiện tổ hợp bit trong một chuỗi bit: Giúp sinh viên biết cách xây dựng máy trạng thái
và thiết kế hệ thông số bằng máy trạng thái

Bài 6: Thực hiện thuật toán FIR dùng cấu trúc FSMD

©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/14
Contents of “Digital Design”
Contents of “Digital Design”

Introduction to the course

Course book

Goal

Exercises and laboratory sessions

Exam

Data representation

Boolean algebra


Logical gates
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/15
Exam
Exam

Close book

Midterm exam: 30%

Final exam: 70%

Completing lab sessions and Homework is a must before taking the exam
©
R.Lauwereins
Imec 2001
Digital

design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/16
Contents of “Digital Design”
Contents of “Digital Design”

Introduction to the course

Data representation

Decimal, Binary, Octal, Hexadecimal

Addition, subtraction, multiplication, division

Negative numbers

Integer, fixed point, fractional, floating point, BCD, ASCII

Boolean algebra

Logical gates
©
R.Lauwereins

Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/17
Contents of “Digital Design”
Contents of “Digital Design”

Introduction to the course

Data representation

Decimal, Binary, Octal, Hexadecimal

Addition, subtraction, multiplication, division

Negative numbers

Integer, fixed point, fractional, floating point, BCD, ASCII

Boolean algebra

Logical gates

©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/18
Decimal
Decimal

1234.56710=

1•1000+2•100+3•10+4•1+5•0.1+6•0.01+7•0.001

1•10
3
+2•10
2
+3•10
1
+4•10
0
+5•10

-1
+6•10
-2
+7•10
-3

r = radix (r = 10), d=digit (0 ≤ d ≤ 9), m = #digits before radix
point (decimal point), n = #digits after decimal point


−=
•=
1m
ni
i
i
rdD
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL

1/19
Binary
Binary

1011.0112=

1•8+0•4+1•2+1•1+0•0.5+1•0.25+1•0.125

1•2
3
+0•2
2
+1•2
1
+1•2
0
+0•2
-1
+1•2
-2
+1•2
-3

r = radix (r = 2), d = digit (0 ≤ d ≤ 1), m = #digits before radix
point (binary point), n = #digits after radix point


−=
•=
1

2
m
ni
i
i
dB
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/20
Octal
Octal

7654.328=

7•512+6•64+5•8+4•1+3•0.125+2•0.015625

7•8
3
+6•8

2
+5•8
1
+4•8
0
+3•8
-1
+2•8
-2

r = radix (r = 8), d = digit (0 ≤ d ≤ 7), m = #digits before radix
point (octal point), n = #digits after radix point


−=
•=
1
8
m
ni
i
i
dO
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial

circuits
Sequential
circuits
FSMD
design
VHDL
1/21
Hexadecimal
Hexadecimal

FEDC.7616=

15•4096+14•256+13•16+12•1+7•1/16+6•1/256

15•16
3
+14•16
2
+13•16
1
+12•16
0
+7•16
-1
+6•16
-2

r = radix (r = 16), d = digit (0 ≤ d ≤ F), m = #digits before radix
point (hexadecimal point), n = #digits after radix point



−=
•=
1
16
m
ni
i
i
dH
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/22
Contents of “Digital Design”
Contents of “Digital Design”

Introduction to the course

Data representation


Decimal, Binary, Octal, Hexadecimal

Addition, subtraction, multiplication, division

Negative numbers

Integer, fixed point, fractional, floating point, BCD, ASCII

Boolean algebra

Logical gates
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/23
3 5
65
728 3
2

carry
x
y
sum 88
010
Binary addition
Binary addition

Binary addition

Decimal addition
carry
x
y
sum
0
1
1
0
0
1
1
1
0
0
1
1
1
1
1

1
1
0
0
1
0
1
0
1
1
1
1
1
1
0
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/24
Binary subtraction

Binary subtraction
x
y
borrow
result
1 1 1 0 1
1 1 1 1
1 1 1 0
0 1 1 1 0
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
1/25
Binary multiplication
Binary multiplication
1 1 1 0
1 1 0 1
1 1 1 0
0 0 0 0
1 1 1 0

1 1 1 0
1 0 1 1 0 1 1 0

Multiplication by repeated add & shift: number of cycles = number of bits of multiplier

Can be implemented in a faster way

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