Programming
Embedded
Systems II

A 10-week course, using C

Michael J. Pont
University of Leicester

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[v2.0]

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Copyright © Michael J. Pont, 2002-2004
This document may be freely distributed and copied, provided that copyright notice at
the foot of each OHP page is clearly visible in all copies.

II


Seminar 1:

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Seminar 2: A flexible scheduler for single-processor embedded systems


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Overview of this seminar
Overview of this course
By the end of the course you’ll be able to …
Main course text
IMPORTANT: Course prerequisites
Review: Why use C?
Review: The 8051 microcontroller
Review: The “super loop” software architecture
Review: An introduction to schedulers
Review: Building a scheduler
Overview of this seminar
The Co-operative Scheduler
Overview
The scheduler data structure and task array
The size of the task array
One possible initialisation function:
IMPORTANT: The ‘one interrupt per microcontroller’ rule!
The ‘Update’ function
The ‘Add Task’ function
The ‘Dispatcher’
Function arguments
Function pointers and Keil linker options
The ‘Start’ function
The ‘Delete Task’ function
Reducing power consumption
Reporting errors
Displaying error codes

Hardware resource implications
What is the CPU load of the scheduler?
Determining the required tick interval
Guidelines for predictable and reliable scheduling
Overall strengths and weaknesses of the scheduler
Preparations for the next seminar

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Seminar 3: Analogue I/O using ADCs and PWM
Overview of this seminar
PATTERN: One-Shot ADC
PATTERN: One-Shot ADC
Using a microcontroller with on-chip ADC
Using an external parallel ADC
Example: Using a Max150 ADC
Using an external serial ADC
Example: Using an external SPI ADC
Overview of SPI
Back to the example …
Example: Using an external I2C ADC
Overview of I2C
Back to the example …
What is PWM?
PATTERN: Software PWM

Preparations for the next seminar

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Seminar 4: A closer look at co-operative task scheduling (and some alternatives)
Overview of this seminar
Review: Co-operative scheduling
The pre-emptive scheduler
Why do we avoid pre-emptive schedulers in this course?
Why is a co-operative scheduler (generally) more reliable?
Critical sections of code

How do we deal with critical sections in a pre-emptive system?
Building a “lock” mechanism
The “best of both worlds” - a hybrid scheduler
Creating a hybrid scheduler
The ‘Update’ function for a hybrid scheduler.
Reliability and safety issues
The safest way to use the hybrid scheduler
Other forms of co-operative scheduler
PATTERN: 255-TICK SCHEDULER
PATTERN: ONE-TASK SCHEDULER
PATTERN: ONE-YEAR SCHEDULER
PATTERN: STABLE SCHEDULER
Mix and match …
Preparations for the next seminar

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Seminar 5: Improving system reliability using watchdog timers

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Overview of this seminar
The watchdog analogy
PATTERN: Watchdog Recovery
Choice of hardware
Time-based error detection
Other uses for watchdog-induced resets
Recovery behaviour
Risk assessment
The limitations of single-processor designs
Time, time, time …
Watchdogs: Overall strengths and weaknesses
PATTERN: Scheduler Watchdog
Selecting the overflow period - “hard” constraints
Selecting the overflow period - “soft” constraints
PATTERN: Program-Flow Watchdog
Dealing with errors

Hardware resource implications
Speeding up the response
PATTERN: Reset Recovery
PATTERN: Fail-Silent Recovery
Example: Fail-Silent behaviour in the Airbus A310
Example: Fail-Silent behaviour in a steer-by-wire application
PATTERN: Limp-Home Recovery
Example: Limp-home behaviour in a steer-by-wire application
PATTERN: Oscillator Watchdog
Preparations for the next seminar

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Seminar 6: Shared-clock schedulers for multi-processor systems
Overview of this seminar
Why use more than one processor?
Additional CPU performance and hardware facilities
The benefits of modular design
The benefits of modular design
So - how do we link more than one processor?
Synchronising the clocks
Synchronising the clocks
Synchronising the clocks - Slave nodes
Transferring data
Transferring data (Master to Slave)
Transferring data (Slave to Master)
Transferring data (Slave to Master)
Detecting network and node errors
Detecting errors in the Slave(s)
Detecting errors in the Master
Handling errors detected by the Slave
Handling errors detected by the Master

Enter a safe state and shut down the network
Reset the network
Engage a backup Slave
Why additional processors may not improve reliability
Redundant networks do not guarantee increased reliability
Replacing the human operator - implications
Are multi-processor designs ever safe?
Preparations for the next seminar

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Seminar 7: Linking processors using RS-232 and RS-485 protocols
Review: Shared-clock scheduling
Overview of this seminar
Review: What is ‘RS-232’?
Review: Basic RS-232 Protocol
Review: Transferring data to a PC using RS-232
PATTERN: SCU SCHEDULER (LOCAL)
The message structure
Determining the required baud rate
Node Hardware
Network wiring
Overall strengths and weaknesses
PATTERN: SCU Scheduler (RS-232)
PATTERN: SCU Scheduler (RS-485)
RS-232 vs RS-485 [number of nodes]
RS-232 vs RS-485 [range and baud rates]
RS-232 vs RS-485 [cabling]
RS-232 vs RS-485 [transceivers]
Software considerations: enable inputs
Overall strengths and weaknesses

Example: Network with Max489 transceivers
Preparations for the next seminar

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Seminar 8: Linking processors using the Controller Area Network (CAN) bus

Overview of this seminar
PATTERN: SCC Scheduler
What is CAN?
CAN 1.0 vs. CAN 2.0
Basic CAN vs. Full CAN
Which microcontrollers have support for CAN?
S-C scheduling over CAN
The message structure - Tick messages
The message structure - Ack messages
Determining the required baud rate
Transceivers for distributed networks
Node wiring for distributed networks
Hardware and wiring for local networks
Software for the shared-clock CAN scheduler
Overall strengths and weaknesses
Example: Creating a CAN-based scheduler using the Infineon C515c
Master Software
Slave Software
What about CAN without on-chip hardware support?
Preparations for the next seminar

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Seminar 9: Applying “Proportional Integral Differential” (PID) control
Overview of this seminar
Why do we need closed-loop control?
Closed-loop control
What closed-loop algorithm should you use?
What is PID control?
A complete PID control implementation
Another version
Dealing with ‘windup’
Choosing the controller parameters
What sample rate?
Hardware resource implications
PID: Overall strengths and weaknesses
Why open-loop controllers are still (sometimes) useful

Limitations of PID control
Example: Tuning the parameters of a cruise-control system
Open-loop test
Tuning the PID parameters: methodology
First test
Example: DC Motor Speed Control
Alternative: Fuzzy control
Preparations for the next seminar

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