January 2006
1Verilog Digital System Design
Copyright Z. Navabi, 2006
Verilog Digital System Design
Verilog Digital System Design
Z. Navabi, McGraw-Hill, 2005
Z. Navabi, McGraw-Hill, 2005
Chapter 1
Chapter 1
Digital System Design
Digital System Design
Automation with Verilog
Automation with Verilog
Prepared by:
Prepared by:
Homa Alemzadeh
Homa Alemzadeh
January 2006
2Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital System Design
Digital System Design
Automation with Verilog
Automation with Verilog
1.1 Digital Design Flow
1.1 Digital Design Flow
1.1.1 Design entry
1.1.1 Design entry
1.1.2 Testbench in Verilog
1.1.2 Testbench in Verilog

1.1.3 Design validation
1.1.3 Design validation


1.1.4 Compilation and synthesis
1.1.4 Compilation and synthesis


1.1.5 Postsynthesis simulation
1.1.5 Postsynthesis simulation


1.1.6 Timing analysis
1.1.6 Timing analysis


1.1.7 Hardware generation
1.1.7 Hardware generation


1.2 Verilog HDL
1.2 Verilog HDL


1.2.1 Verilog evolution
1.2.1 Verilog evolution


1.2.2 Verilog attributes

1.2.2 Verilog attributes


1.2.3 The verilog language
1.2.3 The verilog language


1.3 Summary
1.3 Summary


January 2006
3Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital System Design
Digital System Design
Automation with Verilog
Automation with Verilog

As the size and complexity of digital systems increase, more computer
As the size and complexity of digital systems increase, more computer
aided design (CAD) tools are introduced into the hardware design
aided design (CAD) tools are introduced into the hardware design
process.
process.

Early simulation and primitive hardware generation tools have given
Early simulation and primitive hardware generation tools have given
way to sophisticated design entry, verification, high-level synthesis,
way to sophisticated design entry, verification, high-level synthesis,

formal verification, and automatic hardware generation and device
formal verification, and automatic hardware generation and device
programming tools.
programming tools.

Growth of design automation tools is largely due to hardware
Growth of design automation tools is largely due to hardware
description languages (HDLs) and design methodologies that are
description languages (HDLs) and design methodologies that are
based on these languages.
based on these languages.

Based on HDLs, new digital system CAD tools have been developed
Based on HDLs, new digital system CAD tools have been developed
and are now widely used by hardware designers.
and are now widely used by hardware designers.

One of the most widely used HDLs is the Verilog HDL.
One of the most widely used HDLs is the Verilog HDL.

Because of its wide acceptance in digital design industry, Verilog has
Because of its wide acceptance in digital design industry, Verilog has
become a must-know for design engineers and students in computer-
become a must-know for design engineers and students in computer-
hardware-related fields.
hardware-related fields.
January 2006
4Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow

Digital Design Flow

FPLD Design Flow
FPLD Design Flow
January 2006
5Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow
Digital Design Flow

FPLD Design Flow
FPLD Design Flow
Design Entry
Design Entry
Phase
Phase
January 2006
6Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow
Digital Design Flow

Digital Design Flow begins with specification of the design at various
Digital Design Flow begins with specification of the design at various
levels of abstraction.
levels of abstraction.



Design entry phase:

Design entry phase:
Specification of design as a mixture of behavioral
Specification of design as a mixture of behavioral
Verilog code, instantiation of Verilog modules, and bus and wire
Verilog code, instantiation of Verilog modules, and bus and wire
assignments
assignments
January 2006
7Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow
Digital Design Flow

FPLD Design Flow
FPLD Design Flow
(Continued)
(Continued)
Presynthesis
Presynthesis
Verification
Verification
January 2006
8Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow
Digital Design Flow

Presynthesis verification:
Presynthesis verification:
Generating testbenches for verification of the

Generating testbenches for verification of the
design and later for verifying the synthesis output
design and later for verifying the synthesis output
January 2006
9Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow
Digital Design Flow

FPLD Design Flow
FPLD Design Flow
(Continued)
(Continued)
Synthesis Process
Synthesis Process
January 2006
10Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow
Digital Design Flow

Synthesis process:
Synthesis process:
Translating the design into actual hardware of a
Translating the design into actual hardware of a
target device (FPLD, ASIC or custom IC)
target device (FPLD, ASIC or custom IC)
January 2006
11Verilog Digital System Design
Copyright Z. Navabi, 2006

Digital Design Flow
Digital Design Flow

FPLD Design Flow (Continued)
FPLD Design Flow (Continued)
Postsynthesis
Postsynthesis
Verification
Verification
January 2006
12Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow
Digital Design Flow

Postsynthesis simulation:
Postsynthesis simulation:
Testing the behavioral model of the design
Testing the behavioral model of the design
and its hardware model by using presynthesis test data
and its hardware model by using presynthesis test data
January 2006
13Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow
Digital Design Flow

FPLD Design Flow (Continued)
FPLD Design Flow (Continued)
January 2006

14Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design Flow
Digital Design Flow

Digital Design Flow ends with generating netlist for an application
Digital Design Flow ends with generating netlist for an application
specific integrated circuits (ASIC), layout for a custom IC, or a
specific integrated circuits (ASIC), layout for a custom IC, or a
program for a programmable logic devices (PLD)
program for a programmable logic devices (PLD)
January 2006
15Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design
Digital Design
Flow
Flow
Hardware
Hardware
Generation
Generation
Design Entry
Design Entry
Testbench in Verilog
Testbench in Verilog
Design Validation
Design Validation
Compilation
Compilation

and Synthesis
and Synthesis
Postsynthesis
Postsynthesis
Simulation
Simulation
Timing
Timing
Analysis
Analysis
Digital Design Flow
Digital Design Flow
January 2006
16Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design
Digital Design
Flow
Flow
Hardware
Hardware
Generation
Generation
Design Entry
Design Entry
Testbench in Verilog
Testbench in Verilog
Design Validation
Design Validation
Compilation

Compilation
and Synthesis
and Synthesis
Postsynthesis
Postsynthesis
Simulation
Simulation
Timing
Timing
Analysis
Analysis
Design Entry
Design Entry
Design Entry
Design Entry
January 2006
17Verilog Digital System Design
Copyright Z. Navabi, 2006
Design Entry
Design Entry

The first step in the design of a digital system
The first step in the design of a digital system

Describing the design in Verilog in a top-down hierarchical fashion
Describing the design in Verilog in a top-down hierarchical fashion



Register Transfer Level (RTL):

Register Transfer Level (RTL):


High-level Verilog designs usually
High-level Verilog designs usually
described at this level
described at this level

Verilog constructs used in RT level design:
Verilog constructs used in RT level design:

procedural statements
procedural statements
for high-level behavioral description
for high-level behavioral description

continuous assignments
continuous assignments


for representing logic blocks, bus
for representing logic blocks, bus
assignments, and bus and input/output interconnect specifications
assignments, and bus and input/output interconnect specifications

instantiation statements
instantiation statements


for using lower-level components in an

for using lower-level components in an
upper-level design
upper-level design


January 2006
18Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design
Digital Design
Flow
Flow
Hardware
Hardware
Generation
Generation
Design Entry
Design Entry
Testbench in Verilog
Testbench in Verilog
Design Validation
Design Validation
Compilation
Compilation
and Synthesis
and Synthesis
Postsynthesis
Postsynthesis
Simulation
Simulation

Timing
Timing
Analysis
Analysis
Testbench in Verilog
Testbench in Verilog
Testbench in Verilog
Testbench in Verilog
January 2006
19Verilog Digital System Design
Copyright Z. Navabi, 2006
Testbench in Verilog
Testbench in Verilog

Simulation and Test of a designed system functionality before
Simulation and Test of a designed system functionality before
Hardware generation
Hardware generation

Detection of design errors and incompatibility of components used
Detection of design errors and incompatibility of components used

in the design
in the design

By generation of a test data and observation of simulation results
By generation of a test data and observation of simulation results

Testbench:
Testbench:

A Verilog module
A Verilog module

Use of high-level constructs of Verilog for:
Use of high-level constructs of Verilog for:

Data Generation
Data Generation

Response Monitoring
Response Monitoring

Handshaking with the design
Handshaking with the design

Inside the Testbench: Instantiation of the design module
Inside the Testbench: Instantiation of the design module

Forms a simulation model together with the design, used by a
Forms a simulation model together with the design, used by a
Verilog simulation engine
Verilog simulation engine
January 2006
20Verilog Digital System Design
Copyright Z. Navabi, 2006
Digital Design
Digital Design
Flow
Flow
Hardware

Hardware
Generation
Generation
Design Entry
Design Entry
Testbench in Verilog
Testbench in Verilog
Design Validation
Design Validation
Compilation
Compilation
and Synthesis
and Synthesis
Postsynthesis
Postsynthesis
Simulation
Simulation
Timing
Timing
Analysis
Analysis
Design Validation
Design Validation
Design Validation
Design Validation
January 2006
21Verilog Digital System Design
Copyright Z. Navabi, 2006
Design Validation
Design Validation


An important task in any digital system design
An important task in any digital system design

The process to check the design for any design flaws
The process to check the design for any design flaws

A design flaw due to:
A design flaw due to:

Ambiguous Problem Specifications
Ambiguous Problem Specifications

Designer Errors
Designer Errors

Incorrect Use of Parts in the Design
Incorrect Use of Parts in the Design

Can be done by:
Can be done by:

Simulation
Simulation

Assertion Verification
Assertion Verification

Formal Verification
Formal Verification

January 2006
22Verilog Digital System Design
Copyright Z. Navabi, 2006
Design Validation
Design Validation
Design
Design
Validation
Validation
Simulation
Simulation
Assertion
Assertion
Verification
Verification
Formal
Formal
Verification
Verification
January 2006
23Verilog Digital System Design
Copyright Z. Navabi, 2006
Simulation
Simulation
Design
Design
Validation
Validation
Simulation
Simulation

Assertion
Assertion
Verification
Verification
Formal
Formal
Verification
Verification
Simulation
Simulation
January 2006
24Verilog Digital System Design
Copyright Z. Navabi, 2006
Simulation
Simulation

Simulation for design validation, done before a design is synthesized
Simulation for design validation, done before a design is synthesized

Also Referred to as RT level, or Pre-synthesis Simulation
Also Referred to as RT level, or Pre-synthesis Simulation

Simulation at RTL level is accurate to the clock level
Simulation at RTL level is accurate to the clock level



The advantage: its speed compared with simulations at the gate or
The advantage: its speed compared with simulations at the gate or
transistor levels

transistor levels

The Required Test data: generated graphically using waveform editors,
The Required Test data: generated graphically using waveform editors,
or through a testbench
or through a testbench

Outputs of simulators:
Outputs of simulators:

Waveforms (for visual inspection)
Waveforms (for visual inspection)

Text for large designs for machine processing
Text for large designs for machine processing
January 2006
25Verilog Digital System Design
Copyright Z. Navabi, 2006
Simulation
Simulation

Using a Testbench or a Waveform Editor for Simulation
Using a Testbench or a Waveform Editor for Simulation
Two
Two
alternatives
alternatives
for defining
for defining
test input

test input
data for a
data for a
simulation
simulation
engine
engine
Inputs
Inputs
Outputs
Outputs