HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY
AND EDUCATION
FACULTY OF HIGH-QUALITY TRAINING

VLSI Circuits Design
REPORT

SIMULATE 8-BIT OPERATION MUX,
SUBTRACTOR
Instructor: PhD Pham Van Khoa
Students: Đỗ Hồng Quân-19161049
Vũ Đức Thoại-19161029
Trương Thị Bích Chi-19161044
Lương Ngọc Phương Quỳnh19161050
Nguyễn Phúc Tiến-19161030
Vũ Ngọc Phương Nam-19161039

Tp.HCM, December 2021


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HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND
EDUCATION
FACULTY OF HIGH-QUALITY TRAINING

VLSI Circuits Design
REPORT

SIMULATE 8-BIT OPERATION MUX,
SUBTRACTOR

Instructor: PhD Pham Van Khoa
Students: Đỗ Hồng Quân-19161049
Vũ Đức Thoại-19161029
Trương Thị Bích Chi-19161044
Lương Ngọc Phương Quỳnh19161050
Nguyễn Phúc Tiến-19161030
Vũ Ngọc Phương Nam-19161039

Tp.HCM, December 2021


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INSTRUCTOR’S COMMENTS
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Group Info:
•
•
•
•
•
•

Trương Thị Bích Chi[]
Lương Ngọc Phương Quỳnh[]
Đỗ Hồng Qn []
Nguyễn Phúc Tiến[]
Vũ Đức Thoại[]
Vũ Ngọc Phương Nam[]

Distribution:





Logic Gates

Trương Thị Bích Chi: 100%
Subtractor 8-bit
Nguyễn Phúc Tiến: 33,333% (Half-Sub)
Đỗ Hồng Quân: 33,333% (Full-Sub)
Vũ Đức Thoại: 33,333% (Subtractor 8-bit)
MUX 8-bits
Lương Ngọc Phương Quỳnh: 50%
Vũ Ngọc Phương Nam: 50%
INTRODUCTION
Technology is progressing, particularly in the semiconductor industry.

Smaller and smaller technologies provide more ease while also conserving
energy. This progress is the initial step for the rapid advancement of other
disciplines. With two primary designs: 8-bit Subtractor and 8-bit Mux, we will
demonstrate the potential of 90nm technology in this project.
We make logic gates out of fundamental transistors like PMOS and
NMOS and integrate them into logic circuits like Subtractor and Mux.
Binary subtraction is the fundamental capability of this 8-bit subtractor.
As we all know, today's computers exchange and calculate binary numbers,
therefore binary subtraction is also a necessary component for processing
numeric data.


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Multiplexer is another issue included in the project. By connecting the
multiplexer's single output to the demultiplexer's single input, multiplexers can
save connections on a single channel.
Use Cadence simulation software to validate the project's validity
utilizing the knowledge gained and external knowledge. We expect that the

Subtractor and Mux project will shed light on the benefits of 90nm technology
as well as the fundamental functions of Subtractor and Mux.
We also wish to express our gratitude and admiration to PhD Pham Van
Khoa for his invaluable assistance during the project's execution.


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TABLE OF CONTENT


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LIST FIGURE

Chapter 1:
Chapter 3:


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CHAPTER 1: LOGIC GATE
1. Overview
A logic gate is an idealized model of computation or physical electronic device
implementing a Boolean function, a logical operation performed on one or
more binary inputs that produces a single binary output. Depending on the context, the
term may refer to an ideal logic gate, one that has for instance zero rise time and
unlimited fan-out, or it may refer to a non-ideal physical device (see Ideal and real opamps for comparison).
Logic gates are primarily implemented using diodes or transistors acting
as electronic switches, but can also be constructed using vacuum tubes,

electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules,
or even mechanical elements. With amplification, logic gates can be cascaded in the
same way that Boolean functions can be composed, allowing the construction of a
physical model of all of Boolean logic, and therefore, all of the algorithms
and mathematics that can be described with Boolean logic.
Logic circuits include such devices as multiplexers, registers, arithmetic logic
units (ALUs),
and computer
memory,
all
the
way
up
through
complete microprocessors, which may contain more than 100 million gates. In modern
practice, most gates are made from MOSFETs (metal–oxide–semiconductor fieldeffect transistors).
Compound logic gates AND-OR-Invert (AOI) and OR-AND-Invert (OAI) are
often employed in circuit design because their construction using MOSFETs is simpler
and more efficient than the sum of the individual gates
1. Several logics gates
2.1 AND gate
2.1.1 Theoretical content
The AND gate is a basic digital logic gate that implements logical conjunction
from mathematical logic – it behaves according to the truth table above. A HIGH
output (1) results only if all the inputs to the AND gate are HIGH (1). If none or not all
inputs to the AND gate are HIGH, LOW output results. The function can be extended
to any number of inputs.
Truth table:

Outputs


Inputs
A
0
0
1
1

B
0
1
0
1

Q
0
0
0
1

Q = A.B


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Figure 1.1.AND gate schematic
Figure 1.1. AND gate wavefrom
2.1.2 Simulation

Figure 1.3.Simulate AND gate delay LH

TpLH = 26.00 ps


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Figure 1.4.Simulate AND gate delay HL
TpHL = 26.23 ps

2.1.3. Power
Va = Vb = 1v
Fa = 50Mhz, Fb =100 Mhz

Result simulation average power

2.2 OR gate
2.2.1 Theoretical content
The OR gate is a digital logic gate that implements logical disjunction (∨)
from mathematical logic. A HIGH output (1) results if one or both the inputs to the
gate are HIGH (1). If neither input is high, a LOW output (0) results. In another sense,
the function of OR effectively finds the maximum between two binary digits, just as
the complementary AND function finds the minimum.
Truth table:
Inputs
A
0
0
1
1

B

0
1
0
1

Outputs
Q
0
1
1
1

Q = A+B


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Figure 1.5. OR gate schematic
2.2.2 Simulation

Figure 1.6.OR gate wavefrom


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Figure 1.7. OR gate dalay LH
TpLH=38.85ps

Figure 1.8. OR gate delay HL
TpHL=20.72ps


Tpd=
2.2.3. Power


13
Va = Vb = 1v
Fa = 50Mhz, Fb =100 Mhz
Result simulation average power

2.3. XOR gate
2.3.1 Theoretical content
XOR gate is a digital logic gate that gives a true (1 or HIGH) output when
number of true inputs is odd. An XOR gate implements an exclusive from
mathematical logic; that is, a true output results if one, and only one, of the inputs to
the gate is true. If both inputs are false (0/LOW) or both are true, a false output results.
XOR represents the inequality function, i.e., the output is true if the inputs are not
alike otherwise the output is false. A way to remember XOR is "must have one or the
other but not both".
Truth table:
Inputs
A
0
0
1
1

B
0
1

0
1

Outputs
Q
0
1
1
0

Figure 1.9.XOR gate schematic
2.3.2 Simulation


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Figure 1.10. XOR gate wavefrom

Figure 1.11. XOR gate delay HL
TpHL=56.60ps


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Figure 1.12. XOR gate delay LH
TpLH=65.28ps

2.3.3. Power
Va = Vb = 1v
Fa = 50Mhz, Fb =100 Mhz

Result simulation average power


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CHAPTER 2: SUBSTRACTOR
1. Overview
First, we refer to the adder circuit. An adder is a digital circuit that performs
the addition of numbers. In many computers and other kinds of processors, adders are
used in the rithmetic logic units or ALU. They are also used in other parts of the
processor, where they are used to calculate addresses, table indices, increment and
decrement operators and similar operations.
In electronics, a subtractor can be designed using the same approach as that of
an adder. As with an adder, in the general case of calculations on multi-bit numbers,
three bits are involved in performing the subtraction for each bit of the difference: the
minuend Xi, subtrahend Yi and a borrow in from the previous (less significant) bit
order position Bi. The outputs are the difference bit D i and borrow bit Bi+1 The
subtractor is best understood by considering that the subtrahend and both borrow bits
have negative weights, whereas the X and D bits are positive.

2. Half-subtractor
2.1. Theoretical content
The half subtractor is a combinational circuit that is used to perform subtraction
of two bits. It has two inputs, the minuend X and subtrahend Y, and two outputs the
difference D and borrow out Bout . The borrow out signal is set when the subtractor
needs to borrow from the next digit in a multi-digit subtraction. That is, B out = 1 when
X < Y Since X and Y are bits, Bout = 1 if and only if X = 0 and Y = 1. An important


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point worth mentioning is that the half subtractor diagram aside implements X – Y and
Y – X since Bout on the diagram is given by:
The truth table for the half subtractor is:
Inputs
X
0
0
1
1

Y
0
1
0
1

Outputs
D
Bout
0
0
1
1
1
0
0
0

Therefore the equation is:


Figure 2.1. Half-subtractor schematic


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Figure 2.2. Half-subtractor symbol

2.2. Simulation

Figure 2.3. Half-Subtractor wavefrom

Figure 2.4. Half-Subtractor LH delay


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TpLH = 521,157 ps

Figure 2.5. Half-Subtractor HL delay
TpHL = 453,164 ps

=

Figure 2.6. Wattage Half-Subtractor

Result simulation average power
Va = Vb = 1v
Fa = 50Mhz, Fb = 100 Mhz


3. Full subtractor
3.1 Theoretical content
The full subtractor is a combinational circuit which is used to perform
subtraction of three input bits: the minuend X, subtrahend Y, and borrow in B in. The


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full subtractor generates two output bits: the difference D and borrows out B out. Bin is
set when the previous digit is borrowed from X. Thus, Bin is also subtracted from X is
also subtracted from Y. Or in symbols: X – Y – B in. Like the half subtractor, the full
subtractor generates a borrow out when it needs to borrow from the next digit. Since
we are subtracting Y and Bin from X, a borrow out needs to be generated when
X < Y + Bin. When a borrow out is generated, 2 is added in the current digit. (This is
similar to the subtraction algorithm in decimal. Instead of adding 2, we add 10 when
we
borrow.)
Therefore,
D
=
X
–
Y
–
B in
+
2Bout
The truth table for the full subtractor is:
X
0

0
0
0
1
1
1
1

Inputs
Y
0
0
1
1
0
0
1
1

Outputs
Bin
0
1
0
1
0
1
0
1


D
0
1
1
0
1
0
0
1

Bout
0
1
1
1
0
0
0
1

Therefore the equation is:

Figure 2.7. Full-Subtractor schematic


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Figure 2.8. Full-Subtractor symbol
3.2 Simulation


Figure 2.9. Full-Subtractor wavefrom


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Figure 2.10. Full-Subtractor delay LH
TpLH = 88,03 ps

Figure 2.11. Full-Subtractor delay HL
TpHL = 219,76 ps

=
Figure 2.12. Wattage FullSubtractor
Result simulation average
power
Va = Vb = 2v
Fa = 25 Mhz, Fb = 50 Mhz


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4. Subtractor 8-bit simulation

Figure 2.13. Subtractor 8-bit schematic

Figure 2.14. Subtractor 8-bit symbol


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Figure 2.1. Subtractor 8-bit wavefrom a input

Figure 2.2. Subtractor 8-bit wavefrom b input

Figure 2.3. Subtractor 8-bit wavefrom D and Bout


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Figure 2.4. Wattage Subtractor 8-bit
Result simulation average power